PSRAM Refresh Control via Word Line Segmentation
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Solution Overview
Problem
PSRAM devices experience inefficiencies and increased power consumption due to interruptions in burst read/write operations caused by periodic refresh operations, especially at low frequencies, making them unsuitable for IoT applications.
Innovation Solution
A memory device with a word line arbitrator and refresh controller that segments the word line signal based on a burst length setting value, allowing for selective provision of refresh trigger signals in synchronous or smart refresh modes, enabling efficient refresh operations without interrupting burst access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed in PSRAM, then memory data retention is maintained, but burst read/write operations are interrupted and power consumption increases
Solution Approach 1:
The word line signal is segmented into multiple sub-word line signals based on the burst length setting value. This segmentation allows the refresh controller to selectively activate only the necessary segments during refresh operations, enabling refresh to occur without interrupting the entire burst access sequence. The segmented approach divides the memory access timeline into manageable portions that can be independently controlled.
Solution Approach 2:
The refresh controller performs refresh operations in advance during idle periods within the burst access sequence, before the actual data access is needed. By anticipating when refresh is required and performing it during natural gaps in the access pattern, the system maintains data retention without causing interruptions to the burst read/write operations.
2Reliability
If periodic refresh operations are performed in PSRAM, then memory data retention is maintained, but power consumption increases
Solution Approach 1:
The word line signal is segmented into multiple sub-word line signals based on the burst length setting value. This segmentation allows the refresh controller to selectively activate only the necessary segments during refresh operations, enabling refresh to occur without interrupting the entire burst access sequence. The segmented approach divides the memory access timeline into manageable portions that can be independently controlled.
Solution Approach 2:
Instead of performing full refresh operations on the entire word line, the system performs partial refresh operations on only the necessary segments of the word line. This partial action approach refreshes only the portions of memory that require it, reducing the overall power consumption compared to traditional full refresh operations while still maintaining data retention reliability.
3Use of energy by stationary object
If PSRAM operates at low frequency, then power consumption is reduced, but burst access efficiency decreases and refresh operations cause interruptions
Solution Approach 1:
The system dynamically adjusts its operation mode based on the burst length setting value and access patterns. The word line arbitrator and refresh controller work together to dynamically segment the word line signal and selectively perform refresh operations only when necessary, allowing the PSRAM to maintain high burst access efficiency even at low frequencies where traditional refresh operations would cause interruptions.
Solution Approach 2:
The segmented word line signal enables continuous burst access operations without interruption by coordinating refresh operations to occur during natural idle periods within the burst sequence. This continuity approach ensures that the useful action of data access proceeds uninterrupted while refresh operations are seamlessly integrated into the access timeline, maintaining both low power consumption and high efficiency.
Data Source
AI summary
A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.