3D Memory Conductive Spacer Structure for Lower Interface Traps
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in increasing the lifespan of memory arrays due to high interface trap densities, which limit the number of read/write cycles and device endurance.
Innovation Solution
A three-dimensional memory array design featuring transistors with an insulating memory film as a gate dielectric and a work function material between the word line and the insulating memory film, reducing interface traps and enhancing adhesion, thereby increasing the memory array's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional memory structures are used, then manufacturing is simpler, but interface trap density is high which limits device lifespan
Solution Approach 1:
A conductive spacer is introduced as an intermediary component between the word line and the insulating memory film. This conductive spacer acts as a mediator that reduces interface traps at the critical interfaces, thereby improving device reliability and extending memory array lifespan without complicating the overall manufacturing process
Solution Approach 2:
The gate electrode structure is formed as a composite of multiple materials: a first conductive material for the word line, a second conductive material for the conductive spacer with different work function, and an insulating memory film. This composite structure allows optimization of each interface separately, reducing interface trap density while maintaining electrical performance
2Reliability
If work function material is added between word line and insulating memory film, then adhesion is improved and interface traps are reduced, but device structure becomes more complex
Solution Approach 1:
The conductive spacer serves multiple functions simultaneously: it acts as an adhesion layer between the word line and insulating memory film, provides work function tuning to reduce interface traps, and serves as part of the gate electrode structure. By merging these functions into a single component, the patent improves reliability without proportionally increasing device complexity
Solution Approach 2:
The conductive spacer is designed to perform multiple roles: improving adhesion, reducing interface traps through work function modulation, and contributing to the gate electrode's electrical function. This multi-functionality allows the patent to enhance reliability while keeping the structural complexity increase minimal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces interface traps, allowing for more read/write cycles and increasing the lifespan of the memory array by improving the adhesion between the word line and the insulating memory film, thus enhancing the performance and reliability of the memory array.
Implementation Method 1
enhancing the adhesion between the word line and the insulating memory film
Data Source
AI summary
In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.