FeFET Memory Gate Biasing for Faster Read-After-Write
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric field effect transistors (FeFETs) face speed limitations due to the requirement for a read-after-write delay, which is limited by the rate of charge neutralization of interfacial states after polarization of the ferroelectric layer, leading to a relatively long delay between writing and reading the device state.
Innovation Solution
Applying a non-zero bias voltage with opposite polarity to the gate electrode of the FeFET device after writing, followed by a delay time, significantly reduces the neutralization time constant for trap states, allowing for faster determination of the device state during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write operation is performed on the FeFET device to establish a state, then the data is written successfully, but a long delay is required before reading the state due to charge neutralization of interfacial states
Solution Approach 1:
The patent applies a preliminary action by performing a read operation immediately after the write operation to detect and compensate for charge neutralization effects. This preliminary read allows the system to measure the extent of charge neutralization that occurs during the write operation, and subsequently adjust the read voltage or interpretation of read results to compensate for this effect, thereby enabling accurate state reading without requiring a long delay period
Solution Approach 2:
The patent implements a feedback mechanism where the result of the read operation is used to determine the actual state of the FeFET device, taking into account the charge neutralization that occurs during the write operation. The system uses the read result feedback to correctly interpret the device state, compensating for the charge neutralization effect and enabling accurate reading immediately after writing without requiring prolonged delay time
2Loss of time
If the read operation is performed immediately after write operation, then the delay time is reduced, but the state reading may be inaccurate due to ongoing charge neutralization
Solution Approach 1:
The patent uses feedback from the read operation to correctly interpret the device state. By measuring the read current or voltage and comparing it against expected values that account for charge neutralization effects, the system can accurately determine the device state even when reading immediately after writing. The feedback mechanism allows the system to compensate for the ongoing charge neutralization and extract the correct state information
Solution Approach 2:
The patent introduces an intermediary compensation mechanism that mediates between the write operation and state reading. This intermediary process involves measuring the read characteristics and using this information to compensate for charge neutralization effects, allowing accurate state determination without requiring the system to wait for charge neutralization to complete. The intermediary compensation layer enables accurate reading by translating the affected read signals into correct state information
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the read after write wait time by several orders of magnitude, making it suitable for high-performance memory applications by ensuring accurate state reading without prolonged delays.
Implementation Method 1
FeFETs may be utilized in memory and neuromorphic applications... due to its low operation voltages, low energy consumption, ultra-fast write speeds during program and erase
Implementation Method 2
changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity... to reduce neutralization of a trap state
Data Source
AI summary
A method of writing data to a Ferroelectric-FET (FeFET) based non-volatile memory device can be provided by applying a voltage pulse at a write voltage level with a write polarity at a gate electrode of a FeFET device with reference to a source electrode of the FeFET device, as a write operation to the FeFET device to establish a state for the FeFET device, changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity, at the gate electrode with reference to the source electrode for a delay time to reduce neutralization of a trap state associated with the write operation of the FeFET device, and changing the voltage pulse, after the delay time, to a read voltage level as a read operation to the FeFET device to determine the state of the FeFET device established during the write operation.