Four-Node Latch Circuit for Soft-Error-Resistant Read Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Latch circuits in semiconductor devices are prone to soft errors due to cosmic rays, leading to unintended changes in stored data, especially during read operations where data can be lost due to charge inversion.
Innovation Solution
A latch circuit design that includes first to fourth storage nodes connected to PMOS and NMOS transistor pairs, with a first connection unit connecting a data bus to one storage node during read and write operations, and additional second connection units connecting the data bus to other storage nodes during write operations, ensuring data integrity by preventing simultaneous changes across multiple storage nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple storage nodes are connected to the data bus during read operations, then data transfer speed is improved, but data integrity deteriorates due to charge inversion causing unintended data changes
Solution Approach 1:
The patent divides the connection control into separate stages: a first connection unit connects one storage node to the data bus for read operations, while second connection units connect additional storage nodes only during write operations. This segmentation prevents multiple storage nodes from being simultaneously connected during reads, eliminating charge inversion issues while maintaining data transfer capability.
Solution Approach 2:
The patent implements dynamic connection control where the connection configuration changes based on operation type. During read operations, only the first connection unit is active connecting one storage node. During write operations, second connection units are activated to connect additional storage nodes. This dynamic adjustment optimizes both data integrity during reads and write efficiency during writes.
2Power
If strong driving force is applied to data lines during read operations, then data transfer capability is improved, but data loss occurs due to charge inversion in storage nodes
Solution Approach 1:
The patent applies preliminary anti-action by preventing the harmful connection configuration before it can cause damage. The control logic ensures that during read operations, only one storage node is connected to the data bus through the first connection unit, while second connection units remain inactive. This prevents strong driving forces from causing charge inversion in multiple storage nodes simultaneously, thereby preventing data loss before it can occur.
Solution Approach 2:
The patent introduces connection units as intermediary control elements between the data bus and storage nodes. These intermediaries (first connection unit and second connection units) regulate the connection state based on operation type, acting as mediators that prevent direct harmful interactions between strong data line driving forces and multiple storage nodes during read operations.
3Productivity
If all storage nodes are connected to the data bus during write operations, then write efficiency is improved, but device complexity increases due to additional connection units
Solution Approach 1:
The first connection unit serves multiple functions: it enables read operations by connecting one storage node to the data bus, and it also participates in write operations by working alongside second connection units. This multi-functionality reduces the need for completely separate connection circuits for read and write operations, thereby reducing overall device complexity while maintaining high write efficiency.
Data Source
AI summary
A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.