Fast-Bypass Memory Latch for Lower Clock-to-Output Lag
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Solution Overview
Problem
High-speed digital microarchitectures face limitations in data throughput due to data-to-output lag in memory circuits, which can be exacerbated by clock skew, jitter, and within-die delay variations, leading to logic errors, and existing time-borrowing concepts are not applicable to all memory circuits.
Innovation Solution
A novel fast-bypass memory circuit design that includes a flip-flop with selection logic to bypass logic stages, utilizing a clocked sense-amplifier latch and an unclocked RS-type latch, allowing data to be presented at the output before storage, thereby reducing clock-to-output lag and making the circuit amenable to time borrowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data flows through sequential logic memory circuits (flip-flops), then data storage and synchronization are achieved, but data-to-output lag (tDQ) increases, limiting data throughput
Solution Approach 1:
The memory circuit is segmented into two independent paths: a fast bypass path that directly transmits data from input to output, and a storage path that routes data through flip-flop logic stages. The bypass path is activated when storage is not required, eliminating the data-to-output lag associated with sequential logic while maintaining the option for synchronized storage when needed.
Solution Approach 2:
The circuit dynamically switches between two operational modes: fast-bypass mode for maximum throughput and storage mode for data synchronization. This dynamic behavior allows the same circuit to adapt to different performance requirements, providing short tDQ when speed is critical and enabling reliable storage when data synchronization is required.
2Productivity
If clock speed is increased to improve data throughput, then productivity increases, but clock skew, jitter, and within-die delay variations cause logic errors
Solution Approach 1:
The fast bypass path is prepared in advance and can be activated immediately when needed, providing a pre-established alternative route that avoids the timing-critical paths through sequential logic stages. This preliminary preparation of the bypass path allows high-speed operation without being constrained by clock timing variations.
Solution Approach 2:
The bypass path acts as an intermediary route that mediates between the input and output when the primary storage path would be too slow or unreliable. This intermediary path allows data to bypass the clock-dependent sequential logic stages, eliminating the harmful effects of clock skew and jitter on critical data paths.
3Reliability
If time borrowing is implemented to absorb clock skew and jitter, then reliability improves, but it is not applicable to all memory circuit types
Solution Approach 1:
The fast-bypass memory circuit design provides universal applicability across different memory circuit types by combining bypass logic with standard flip-flop structures. The same basic architecture can be applied to various memory configurations, making the time-borrowing capability universally applicable rather than limited to specific memory types.
Data Source
AI summary
A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.