SRAM Read Multiplexer Replica Transistors for Voltage Difference Loss
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Solution Overview
Problem
Prior SRAM memory circuits experience voltage difference (Vdiff) loss due to parasitic capacitance, leading to errors during bit line read operations, as the discharge current through parasitic capacitance affects the node voltages, causing an undesirable reduction in the voltage difference between INP and INN nodes.
Innovation Solution
Incorporation of replica transistors that are always off when their corresponding columns are selected, which provide equivalent parasitic capacitance to compensate for the voltage difference loss by maintaining node voltages at VDD, thereby reducing errors in bit line read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistors are turned off to deselect a column, then power consumption is reduced and column isolation is achieved, but parasitic capacitance causes voltage difference loss on bit lines
Solution Approach 1:
A replica transistor is introduced as an intermediary component that mimics the parasitic capacitance effect of the turned-off transistor. The replica transistor remains in the on-state and provides a compensating current that counteracts the voltage difference loss caused by parasitic capacitance, thereby maintaining bit line voltage accuracy without requiring the main transistor to remain on.
Solution Approach 2:
The invention creates a copy (replica) of the transistor structure with identical parasitic capacitance characteristics. This replica transistor is configured to always remain on and provides a compensating current that replicates the effect needed to offset the parasitic capacitance discharge, thereby copying the beneficial electrical characteristic without the harmful side effect of continuous power consumption.
2Reliability
If transistors remain on to maintain bit line voltage, then voltage difference accuracy is maintained, but power consumption increases
Solution Approach 1:
The replica transistor serves as a mediator that handles the voltage compensation function separately from the main transistor. This allows the main transistor to be turned off for power savings while the replica transistor provides the necessary voltage difference maintenance through its compensating current, effectively separating the power consumption function from the voltage accuracy function.
Solution Approach 2:
The voltage compensation function is extracted from the main transistor and assigned to a separate replica transistor. This extraction allows the main transistor to be fully turned off during column deselection, eliminating its power consumption, while the replica transistor handles only the voltage accuracy maintenance with minimal power impact.
3Reliability
If parasitic capacitance is minimized to reduce voltage loss, then bit line stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Instead of trying to eliminate parasitic capacitance, the invention converts this harmful effect into a beneficial one by creating a replica transistor that intentionally introduces an equal amount of parasitic capacitance. This replica capacitance is used to generate a compensating current that offsets the original parasitic capacitance loss, thereby turning the manufacturing challenge into a functional advantage.
Solution Approach 2:
The invention changes the operational state parameter of the transistor from binary (on/off) to a three-state system (on, off, and replica always on). The replica transistor is biased to always remain in the on-state, fundamentally changing its operational parameters to enable continuous compensating current flow that counteracts parasitic capacitance effects regardless of the main transistor state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively compensates for Vdiff loss by maintaining node voltages at VDD, reducing errors in bit line read operations and enhancing the reliability of SRAM memory circuits.
Implementation Method 1
there is a parasitic capacitance CP1 between the source of transistor M4 and node INP. As can be seen in FIG. 1B, since cell 53 stores a '0' value so BL1 discharges and due the parasitic capacitance CP1 between BL1 and INP node, node INP does not remain at VDD, but discharges
Data Source
AI summary
A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.