Step Dielectric Ferroelectric Memory for Multi-Level Bit Storage
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Solution Overview
Problem
The increasing number of memory cells in memory devices leads to larger device sizes and higher manufacturing costs, necessitating the development of multi-level bit cells to enhance storage capacity while minimizing costs.
Innovation Solution
A ferroelectric memory device with a multi-level bit cell, featuring a field effect transistor with a step dielectric structure, comprising a substrate, source and drain regions, and a gate structure with oxide and ferroelectric layers of varying thicknesses, allowing for the storage of multiple bits of data by manipulating the polarization states of the ferroelectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to enhance storage capacity, then storage capacity is improved, but device size increases and manufacturing costs increase
Solution Approach 1:
The patent introduces a vertical dimension by stacking multiple ferroelectric layers (first ferroelectric layer, second ferroelectric layer, third ferroelectric layer) with different thicknesses to create multi-level storage. This allows multiple bits of data to be stored in a single bit cell by varying the thickness of ferroelectric portions, effectively transitioning from planar to three-dimensional storage architecture to increase storage capacity without proportionally increasing device area
Solution Approach 2:
The gate structure is segmented into multiple distinct portions: gate electrode, first ferroelectric layer, second ferroelectric layer, and third ferroelectric layer. Each layer can be independently controlled with different voltages, allowing individual bits to be written and read. This segmentation enables parallel operation of multiple storage elements within a compact structure
2Quantity of substance
If the number of memory cells is increased to enhance storage capacity, then storage capacity is improved, but manufacturing costs increase
Solution Approach 1:
Multiple storage elements are merged into a single integrated bit cell structure. The first, second, and third ferroelectric layers are formed in the same fabrication process sequence, and all gate portions share common source and drain regions. This merging reduces the number of discrete components and interconnections required, thereby reducing manufacturing complexity and cost per bit
3Quantity of substance
If multi-level bit cell with varying thickness layers is implemented, then storage capacity per area is improved, but device complexity increases
Solution Approach 1:
Different regions of the gate structure have locally optimized properties: the first ferroelectric layer has a first thickness, the second ferroelectric layer has a second thickness, and the third ferroelectric layer has a third thickness. Each layer can be independently tailored to store specific bit information. This local differentiation of thickness enables multi-level storage while maintaining a regular, repeating pattern that simplifies fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the storage of multiple bits of data in a compact form, reducing the cost per bit area and increasing storage capacity, while maintaining efficient data retention and read/write operations.
Implementation Method 1
a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions, wherein at least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction
Data Source
Figure 1~2
Figure 3A~3B
Figure 4~5
AI summary
A ferroelectric memory device (100) includes a substrate (110) including a source region (120) and a drain region (130), and a gate structure (140) disposed over the substrate. The gate structure includes a gate electrode (146) including a plurality of electrode portions (146', 146'') arranged in a first direction parallel to a top surface of the substrate, an oxide layer (142) including a plurality of oxide portions (142', 142'') corresponding respectively to the plurality of electrode portions, and a ferroelectric layer (144) disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions (144', 144'') corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.