Memory Chip Bus Wiring Using Idle Lines for Power Shielding
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Solution Overview
Problem
The existing wiring configurations in memory chips, such as DRAM, face issues with cross-talk between neighboring wires and voltage drops/glitches in power supply wires due to parasitic couplings, which affect data transmission speed and power integrity, and are challenging to address without increasing production costs or chip area.
Innovation Solution
The solution involves reconfiguring data bus wires and power supply wires by utilizing non-active signal wires as additional power supply wires to reduce effective resistance and inductance, and using these wires as shielding to minimize parasitic couplings, thereby improving power efficiency and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If data bus wires and power supply wires share the same metal layer, then the number of metal layers is reduced and chip area is minimized, but cross-talk between neighboring wires and voltage drop on power supply wires occur due to parasitic couplings
Solution Approach 1:
The patent segments the power supply network by introducing intermediate power supply nodes along the power supply wires. These nodes divide the continuous power supply wire into multiple segments, reducing the parasitic coupling effects between data bus wires and power supply wires. Each segment operates more independently, minimizing voltage drops and cross-talk while maintaining the single-layer configuration.
Solution Approach 2:
The patent introduces intermediate power supply nodes as intermediary elements between the power supply source and the memory arrays. These intermediary nodes act as local power redistribution points, reducing the parasitic coupling effects on the main power supply wires and minimizing voltage drops without requiring additional metal layers.
2Object-affected harmful factors
If power supply wires are placed in a separate metal layer, then cross-talk and parasitic couplings are reduced, but the number of metal layers increases and production cost rises
Solution Approach 1:
The patent makes the data bus wires multi-functional by enabling them to serve dual purposes: data transmission and power supply. During non-data transmission periods, the data bus wires are configured to carry power supply signals to memory arrays, eliminating the need for dedicated separate power supply wires and reducing the total number of metal layers required.
Solution Approach 2:
The patent implements dynamic reconfiguration of wire functions based on operational mode. The data bus wires dynamically switch between data transmission mode and power supply mode, allowing the same physical infrastructure to serve multiple functions at different times, thereby reducing overall system complexity without compromising performance.
3Productivity
If data transmission speed is increased, then productivity improves, but cross-talk effects and voltage drops become more severe due to higher frequency signals
Solution Approach 1:
The patent segments the power supply distribution network into multiple zones with intermediate power supply nodes. This segmentation reduces the parasitic inductance and resistance effects that become more severe at high frequencies, allowing faster data transmission while maintaining power integrity through localized power delivery zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces cross-talk effects and voltage drops/glitches, enhancing the signal-to-noise ratio and overall performance of the memory chip without increasing production costs or chip size.
Implementation Method 1
utilizing non-active signal wires as additional power supply wires to reduce effective resistance and inductance
Implementation Method 2
using these wires as shielding to minimize parasitic couplings
Implementation Method 3
the parasitic capacitance can form between part-to input (gate-to-source and gate-to-bulk) of the transistors belonging to either the driver inverter or receiver inverter. All these parasitic capacitances that form between wire-to-wire electric fields, part-to-input (gate-to-source and gate-to-bulk) electric fields can add up to further exacerbate the voltage-drop problem in the power wires
Data Source
AI summary
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.