Semiconductor Structure Common Bit Line for Sense Amplifier Area Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to improve internal space utilization, reduce the area occupied by sense amplifiers, and simplify the manufacturing process as feature sizes decrease, making it difficult to form densely arranged bit lines and share sense amplifiers in semiconductor structures like DRAM and MRAM.
Innovation Solution
A semiconductor structure with a substrate, memory array, word line structure, and common bit line, where active pillars have channel regions covered by word lines and a common bit line connects all storage cells, simplifying the manufacturing process and reducing the number of sense amplifiers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If densely arranged bit lines are formed in reduced space, then storage cell density is improved, but manufacturing difficulty increases
Solution Approach 1:
Multiple bit lines are merged into a single shared bit line that serves multiple storage cells. The shared bit line is positioned to electrically connect to multiple active pillars through common source/drain regions, reducing the number of separate bit lines needed and simplifying the manufacturing process while maintaining high storage cell density
Solution Approach 2:
The shared bit line performs multiple functions by serving as the bit line for multiple storage cells simultaneously. A single bit line structure provides electrical connection to multiple active pillars, making the bit line system more universal and reducing overall device complexity
2Reliability
If multiple sense amplifiers are deposited for dense bit line arrangement, then bit line functionality is improved, but area occupied by sense amplifiers increases
Solution Approach 1:
Multiple sense amplifier functions are merged into a single shared sense amplifier. The shared sense amplifier is electrically connected to the shared bit line and can service multiple storage cells, eliminating the need for separate sense amplifiers for each bit line and significantly reducing the total area occupied by sense amplifier circuits
Solution Approach 2:
The shared sense amplifier performs multiple sensing functions for different storage cells through the shared bit line connection. A single sense amplifier structure provides universal sensing capability across multiple bit line connections, reducing area while maintaining functionality
3Length of moving object
If feature size is reduced, then device miniaturization is improved, but space for bit lines becomes smaller
Solution Approach 1:
Multiple bit lines are combined into a single shared bit line structure, which occupies less physical space than multiple separate bit lines. This merging allows the bit line system to fit within reduced feature sizes while still providing electrical connection to multiple storage cells arranged in dense configurations
Solution Approach 2:
The bit line and source/drain structures are arranged in three-dimensional configurations with vertical stacking. Active pillars extend in the vertical direction with channel regions at different heights, allowing bit lines to connect to multiple storage cells through vertical rather than only lateral routing, effectively utilizing space in reduced feature size devices
Data Source
AI summary
A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.