Nanostructure SRAM Cell Stress Layout for Read Reliability
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Solution Overview
Problem
In SRAM devices, the equal current conduction of access and pull-down transistors due to similar dimensions leads to read failure during data retrieval, as the design constraints often require them to be of the same size, resulting in insufficient voltage difference for accurate logical state determination.
Innovation Solution
The implementation of nanostructure transistors with shallow metal interconnections for access transistors and deep metal interconnections for pull-down transistors, applying varying stress levels to their conduction channels, allowing the pull-down transistors to conduct higher currents and improve read operation efficiency without compromising design constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If access transistors and pull-down transistors are designed with similar dimensions to meet design constraints, then manufacturing simplicity is maintained, but read operation reliability deteriorates due to insufficient voltage difference
Solution Approach 1:
The patent applies different stress conditions to different transistor types within the same memory cell. Specifically, pull-down transistors are subjected to higher stress levels than access transistors, creating local differentiation in electrical characteristics. This allows the transistors to have similar physical dimensions while achieving different current conduction properties, thereby resolving the contradiction between manufacturing simplicity and read operation reliability
Solution Approach 2:
The patent changes the stress parameter applied to the conduction channels of different transistors. By varying the stress level (a physical parameter) rather than the transistor dimensions, the invention achieves different current conduction characteristics without altering the geometric parameters. This enables pull-down transistors to conduct higher currents than access transistors while maintaining uniform dimensions, thus improving read operation reliability without compromising ease of manufacture
2Productivity
If pull-down transistors are made larger to conduct higher currents, then read operation efficiency improves, but device complexity increases
Solution Approach 1:
Instead of changing the dimensional parameters of pull-down transistors to increase their current conduction capability, the patent changes the stress parameter applied to their conduction channels. This allows achieving higher current conduction (improved read operation efficiency) without modifying the physical size or geometric complexity of the transistors, thereby avoiding increased device complexity
Solution Approach 2:
The patent replaces the traditional approach of using mechanical/geometric differentiation (different transistor sizes) with a physical field-based approach (stress application). By using stress as a control mechanism rather than relying on dimensional variations, the invention achieves differential current conduction without increasing structural complexity, thus improving read operation efficiency while maintaining device simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the current conduction of pull-down transistors, reducing read failure rates by ensuring a sufficient voltage difference can be achieved during data retrieval, thereby improving the reliability of SRAM operations.
Implementation Method 1
applying varying stress levels to their conduction channels, allowing the pull-down transistors to conduct higher currents
Data Source
AI summary
A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.