Resistive-Switching SRAM Cell for Fast Non-Volatile Access
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Solution Overview
Problem
Current memory technologies face challenges in achieving compact, high-speed access to non-volatile data storage while maintaining low power consumption and integration with CMOS technology.
Innovation Solution
A memory cell design incorporating a single resistance switching element and four transistors, where the resistance switching element stores non-volatile data and is programmable between two resistance states, allowing for fast data transfer to volatile storage nodes, enabling quick read and write operations with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory is used for non-volatile data storage, then data retention is improved, but access speed deteriorates and power consumption increases
Solution Approach 1:
The memory system is segmented into two distinct parts: volatile memory for fast data access and a resistance switching element for non-volatile data storage. This segmentation allows each component to perform its specialized function optimally - the volatile memory provides high-speed access while the resistance element maintains data retention, resolving the contradiction between speed and data retention.
2Duration of action of stationary object
If flash memory is used for non-volatile data storage, then data retention is improved, but power consumption increases
Solution Approach 1:
The memory system is segmented into two distinct parts: volatile memory for fast data access and a resistance switching element for non-volatile data storage. This segmentation allows each component to perform its specialized function optimally - the volatile memory provides high-speed access while the resistance element maintains data retention, resolving the contradiction between speed and data retention.
3Speed
If a conventional SRAM cell is used, then access speed is improved, but data retention deteriorates
Solution Approach 1:
The invention merges a conventional SRAM cell structure with a resistance switching element into a unified memory device. The SRAM portion maintains fast access speeds through its established latch-based architecture, while the integrated resistance element adds non-volatile data retention capability. The merging allows both functions to coexist and support each other within a single device.
4Duration of action of stationary object
If more transistors are added to achieve non-volatile storage, then data retention is improved, but device complexity increases
Solution Approach 1:
The resistance switching element serves multiple functions simultaneously: it stores non-volatile data, acts as one transistor in the latch circuit, and provides the necessary control functionality. This multi-functionality reduces the overall transistor count compared to using separate components, as the resistance element replaces what would otherwise be additional transistors needed for non-volatile storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast data access and low power consumption by maintaining non-volatile data through resistance switching elements, allowing for quick loading of programmed states and independent volatile data storage, suitable for applications like field programmable gate arrays.
Implementation Method 1
a single resistance switching element, wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances
Data Source
AI summary
A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.