Resistive Memory Bank Layout for Real-Time Bit Failure Correction
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Solution Overview
Problem
Conventional techniques for handling bit failures in resistive memory arrays, such as MRAM, are slow, time-consuming, and inefficient, as they require multiple memory array accesses and consume valuable space, making real-time repair of failures impractical and potentially inaccurate.
Innovation Solution
The implementation of a single bit repair (SBR) array, which is simultaneously accessible with the resistive memory array, allowing for parallel access and storage of failure indications, thereby enabling real-time correction of bit failures by dividing the memory array into two banks and storing failure addresses at a bit level granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques using OTP NVM arrays are used to store failure information, then failure detection capability is improved, but memory access speed deteriorates due to slow OTP NVM access time
Solution Approach 1:
The patent creates a copy of the failure information from the slow OTP NVM array into a fast register upon system power up. This register copy is then used for real-time memory access operations, eliminating the need to access the slow OTP NVM during normal operation. The copying principle allows the system to maintain reliable failure detection while achieving fast access speeds.
Solution Approach 2:
The patent performs preliminary action by loading failure information from OTP NVM into fast registers during system power up, before any memory access operations occur. This preliminary loading ensures that the failure data is already in fast memory when needed, resolving the speed contradiction without compromising detection capability.
2Reliability
If replacement rows are used to handle failed bit cells, then reliability is improved by providing functional replacements, but memory space utilization deteriorates due to consumption of valuable memory space
Solution Approach 1:
The patent extracts only the essential failure information (addresses of failed bits) from the complete replacement row concept. Instead of allocating entire replacement rows, the system stores only the minimal necessary data (failed bit addresses) in the SBR array. This extraction principle maintains the ability to handle failures while dramatically improving memory space utilization.
Solution Approach 2:
The patent applies local quality by providing repair capability only where needed - at the specific locations of failed bits - rather than allocating entire replacement rows. The SBR array stores addresses of failed bits, and repair is performed locally at those specific addresses, optimizing memory space while maintaining reliability.
3Reliability
If multiple memory array accesses are performed for failure detection and correction, then failure detection accuracy is improved, but time consumption increases making real-time repair impractical
Solution Approach 1:
The patent merges the failure detection and correction operations into a single parallel access to the SBR array. By storing failure addresses in the simultaneously accessible SBR array, the system can detect and correct failures in one operation rather than requiring multiple sequential accesses to the main memory array and OTP NVM, achieving real-time repair while maintaining detection accuracy.
Solution Approach 2:
The patent enables continuous useful action by making the SBR array simultaneously accessible with the resistive memory array. This allows failure detection and correction to occur continuously during normal memory operations without interrupting or pausing the memory access flow, achieving real-time repair capability.
4Ease of repair
If replacement rows are allocated for failed rows, then ease of repair is improved by providing ready-made replacements, but device complexity increases due to additional memory structures
Solution Approach 1:
The patent extracts only the essential repair information (failed bit addresses) from the complex replacement row concept. The SBR array stores minimal data structures containing just the addresses of failed bits, eliminating the need for complex replacement row management while maintaining ease of repair through simple address-based lookup and correction.
Data Source
AI summary
Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.