Staggered Vertical Transistor Memory Cell Design
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high integration density, favorable electrical characteristics, reliability, low power consumption, and novel design in memory devices, particularly in the use of oxide semiconductors for transistors.
Innovation Solution
A memory device design featuring staggered arrangements of vertical transistors with oxide semiconductors, where each transistor has a channel formation region on the side surface of an opening portion within an insulating layer, allowing for a short channel length and long channel width, thereby increasing on-state current and integration density, and utilizing shared conductors for gate and source/drain electrodes to minimize cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in staggered configuration with vertical transistors, then integration density increases, but device complexity increases
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking, utilizing the third dimension (height) to increase integration density. Multiple memory cells are stacked vertically with shared conductors, allowing higher density without proportionally increasing lateral footprint or device complexity
Solution Approach 2:
Adjacent memory cells share common conductors (gate electrodes and source/drain electrodes), reducing the total number of conductors needed. This merging approach increases integration density while actually reducing device complexity by eliminating redundant components
2Power
If channel length is shortened and channel width is extended on side surface, then on-state current increases, but manufacturing precision requirements increase
Solution Approach 1:
The channel is formed on the side surface of the opening portion rather than horizontally, extending the channel width in the vertical direction while maintaining short horizontal length. This dimensional reorientation achieves high on-state current without demanding extreme manufacturing precision
Solution Approach 2:
The channel formation region is nested within the opening portion of the insulating layer, with the gate electrode surrounding it. This nested structure naturally defines the channel dimensions through the opening geometry rather than requiring separate precision patterning steps
3Area of stationary object
If conductors are shared between adjacent memory cells, then cell area decreases, but reliability requirements increase
Solution Approach 1:
Adjacent memory cells share gate electrodes and source/drain electrodes as common conductors, significantly reducing the number of conductors per cell and minimizing cell area. The shared conductors are designed with sufficient cross-section to handle combined current loads, maintaining reliability
Solution Approach 2:
Each conductor serves multiple functions: a gate electrode acts as both the gate for one transistor and the source/drain electrode for the adjacent transistor. This multi-functionality reduces component count and area while the conductor design ensures it can reliably perform all its functions simultaneously
Data Source
AI summary
A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.