Cascode Dual Level Shifter for Metastability-Safe Thin-Oxide FETs
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Solution Overview
Problem
Cascode complementary dual level shifters face issues with metastability and poor p-channel FET pull-up current capability due to low absolute gate-to-source voltage, leading to malfunction or undesired states in thin-oxide FETs, especially in advanced technology nodes like 14 nm where voltage scaling reduces allowable voltages.
Innovation Solution
A level shifter design incorporating specific configurations of p-channel and n-channel FETs, along with condensers, is implemented to manage voltage levels effectively, ensuring that FETs operate within allowable voltage ranges by using a cascode driver with cross-coupled inverter circuits to prevent high voltage application directly to FETs, thereby maintaining device longevity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If cascode complementary dual level shifter is used to shift between regular and high voltage, then voltage level shifting capability is improved, but metastability and poor p-channel FET pull-up current capability occur due to low absolute gate-to-source voltage
Solution Approach 1:
The level shifter is divided into two separate circuit sections: a first circuit section for shifting to a first voltage level and a second circuit section for shifting to a second voltage level. Each section has dedicated p-channel FETs and n-channel FETs configured to handle specific voltage transitions, preventing the metastability issues that occur when a single cascode structure attempts to handle multiple voltage levels simultaneously.
Solution Approach 2:
An inverter is introduced as an intermediary stage between the first and second circuit sections. This inverter acts as a buffer that stabilizes the signal transition between different voltage levels, preventing direct coupling that would cause metastability and ensuring clean logic level transitions.
2Ease of manufacture
If thin-oxide FET only circuits are used to reduce manufacturing and development costs, then manufacturing cost is reduced, but allowable voltage is significantly increased
Solution Approach 1:
The circuit dynamically adjusts the voltage levels applied to the thin-oxide FETs based on operational requirements. By using dual-level shifting with controlled voltage transitions, the circuit ensures that thin-oxide FETs only experience voltage levels within their safe operating range, preventing breakdown while enabling cost-effective manufacturing.
Solution Approach 2:
The invention changes the voltage parameters applied to different parts of the circuit. The first circuit section operates with voltage levels suitable for thin-oxide FETs, while the second circuit section handles higher voltage levels. This parameter separation allows thin-oxide FETs to be used throughout the circuit without exposure to damaging high voltages.
3Productivity
If cross-coupled inverter gate is used, then voltage shifting is achieved, but poor cascade p-channel FET pull-up current capability occurs due to low absolute gate-to-source voltage
Solution Approach 1:
The pull-up current path is segmented into dedicated p-channel FETs in each circuit section. The first circuit section has p-channel FETs optimized for pulling up to the first voltage level, while the second circuit section has p-channel FETs optimized for pulling up to the second voltage level. This segmentation ensures adequate pull-up current capability at each voltage level without requiring excessively large gate-to-source voltages.
Solution Approach 2:
Each circuit section is locally optimized with appropriate transistor sizing and configuration for its specific voltage level. The p-channel FETs in each section have dimensions and biasing tailored to provide sufficient pull-up current for their respective voltage transitions, rather than using a uniform design that would compromise performance at either level.
Data Source
AI summary
A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.