Semiconductor Device Bank Group Control via Synthesis Signal
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently performing column operations and mode register read operations across multiple bank groups, particularly in managing complex pulse signals and selection signals to optimize data transfer and reduce power consumption.
Innovation Solution
The semiconductor device incorporates a synthesis signal generation circuit, column control circuit, and control signal generation circuit to generate and manage bank selection signals and control signals for column operations and mode register read operations, utilizing synchronized pulses and adjusted pulse widths to efficiently select and operate bank groups, thereby optimizing data transfer and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bank groups are supported for parallel data transfer, then productivity is improved, but device complexity increases due to multiple selection signals and pulse management
Solution Approach 1:
The patent combines multiple selection signals (first bank selection signal and second bank selection signal) and multiple read pulses into a unified register synthesis signal that controls a single mode register. This merging approach allows the device to manage multiple bank groups through a single control mechanism, reducing the complexity of signal management while maintaining the ability to perform parallel data transfer operations across different bank groups.
2Measurement precision
If precise pulse timing is implemented for mode register read operations, then measurement precision is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent introduces a register synthesis signal as an intermediary control mechanism that mediates between the multiple read pulses and the mode register. This intermediary signal consolidates the timing control function, allowing precise pulse timing for mode register read operations to be achieved through a single synthesized control signal rather than requiring separate precise timing circuits for each bank group operation.
Data Source
AI summary
A semiconductor device includes a synthesis signal generation circuit, a column control circuit, and a control signal generation circuit. The synthesis signal generation circuit generates a register synthesis signal in response to first and second read pulses sequentially generated during a read operation. The column control circuit generates any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group included in a core circuit in response to the first and second read pulses. The control signal generation circuit generates a control signal for controlling an output operation of a mode register in response to the register synthesis signal.