3D FeFET Memory Stack With Mobility-Tuned Channels for 3-Bit Storage
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has increased complexity in processing and manufacturing, particularly for 3D memory devices, where existing technologies have not fully addressed the challenges of achieving efficient data storage and read operations while minimizing layout area and power consumption.
Innovation Solution
A 3D memory device is designed with ferroelectric field effect transistors (FeFET) that utilize vertically stacked memory cells, featuring oxide semiconductor channel layers with different electron mobilities and ferroelectric layers as gate dielectrics, allowing for distinct threshold voltages and efficient data storage through polarization changes, enabling reduced layout area and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar memory devices are used, then manufacturing process is simpler, but functional density and storage capacity are limited
Solution Approach 1:
The patent transitions from planar (2D) memory device architecture to three-dimensional (3D) stacked architecture. Multiple memory cell layers are vertically stacked above a common substrate, enabling increased functional density by utilizing the vertical dimension for additional storage capacity without proportionally increasing the chip footprint area.
Solution Approach 2:
The patent implements a stacked configuration where multiple memory cell layers are nested vertically. Each memory cell layer contains storage elements that are stacked in tiers, with lower tiers positioned beneath upper tiers. This nesting arrangement allows multiple storage elements to occupy a compact vertical space, increasing density while managing structural complexity through hierarchical organization.
2Quantity of substance
If more memory cells are added to increase storage capacity, then data storage capability improves, but layout area and power consumption increase
Solution Approach 1:
The patent achieves increased storage capacity by stacking memory cell layers vertically in the third dimension. Multiple tiers of storage elements are arranged in a stacked configuration above a common substrate, allowing the device to store more data without proportionally increasing the horizontal chip area. The vertical stacking enables higher density by utilizing z-axis space.
Solution Approach 2:
The patent combines multiple memory cell layers into a single integrated stacked structure. Shared components such as word lines, bit lines, and control circuits are merged across tiers, allowing multiple storage elements to operate from a common base structure. This merging reduces redundant components and minimizes the overall layout area required for the memory device.
3Quantity of substance
If more memory cells are added to increase storage capacity, then data storage capability improves, but power consumption increases
Solution Approach 1:
The patent merges multiple memory cell layers into a stacked architecture where lower and upper tiers share common control circuits, word lines, and bit lines. This sharing of components across tiers reduces the total number of independent control elements required, thereby reducing overall power consumption for a given storage capacity compared to having separate planar memory blocks.
Solution Approach 2:
The patent implements multi-functional shared components that serve multiple tiers simultaneously. Control circuits and signal lines are designed to operate across multiple memory cell layers, allowing a single component to perform multiple functions across different storage tiers. This universality reduces the total component count and associated power consumption while maintaining high storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient data storage and read operations with reduced layout area and power consumption, as only three memory cells with different on-currents are needed to store 3-bit data, enhancing the storage capacity and power efficiency of the 3D memory device.
Implementation Method 1
ferroelectric layers as gate dielectrics, allowing for distinct threshold voltages and efficient data storage through polarization changes
Implementation Method 2
oxide semiconductor channel layers with different electron mobilities
Data Source
AI summary
A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.