Accelerated Output Latch Circuit for Asymmetric Memory Delays
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Solution Overview
Problem
Conventional output latches, such as NAND S-R latches, introduce asymmetric rising and falling transition delays due to sequential NAND gate operations, which hinder memory access speed and computational performance in electronic devices.
Innovation Solution
The implementation of an output latch with first and second output transition circuitries accelerates voltage level transitions at output nodes, bypassing the sequential operation of cross-coupled logic gates to reduce memory access time by utilizing pull-down or pull-up transistors coupled between output nodes and a voltage rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional output latches with sequential NAND gate operations are used, then the circuit structure is simple, but the output transition delays are asymmetric and slow
Solution Approach 1:
The output latch is segmented into separate pull-up and pull-down transition circuits that operate independently. The pull-up circuit accelerates rising transitions while the pull-down circuit accelerates falling transitions, allowing each transition type to be optimized separately rather than being constrained by sequential gate operations
Solution Approach 2:
The pull-up and pull-down circuits are pre-configured with transistors positioned to immediately respond to input changes. When an input voltage changes state, the corresponding pull-up or pull-down circuit is already in place to rapidly drive the output node to the target voltage level without waiting for sequential gate propagation
2Speed
If memory access speed is increased using faster memory types like SRAM, then the memory speed improves, but the cost and chip area increase
Solution Approach 1:
The invention changes the temporal parameter of memory access by reducing output transition delays through accelerated pull-up and pull-down circuits. This allows standard-speed memory cells to achieve effectively faster access times by optimizing the output stage performance, thereby avoiding the need to replace memory cells with faster but more area-intensive SRAM
3Loss of time
If hierarchical memory with cache is implemented, then the average memory access time reduces, but the system complexity increases
Solution Approach 1:
The invention extracts the delay-causing sequential gate operations from the output latch and replaces them with direct pull-up and pull-down transistor circuits. This removes the bottleneck in the memory access path without requiring additional cache memory layers or complex hierarchical structures
Solution Approach 2:
Instead of adding more memory layers to reduce access time, the invention inverts the approach by optimizing the output stage of existing memory to accelerate data retrieval. Rather than bringing data closer through hierarchical caching, the invention makes the data exit the memory cell faster through improved output transition circuitry
Data Source
AI summary
An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node.