Configurable FPGA Local Memory Structure for Flexible Capacity Scaling
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Solution Overview
Problem
Existing FPGA local memory architectures face inefficiencies in designing small- to medium-capacity memory structures, as using registers consumes excessive logic resources and using block memories results in resource wastage.
Innovation Solution
An extensible configurable FPGA storage structure comprising multiple local storage units, a controller, and clock buffers, which generates enable and address decoding signals to optimize data input and output based on various configuration modes, reducing resource consumption and wastage by sharing signal inputs and using a multiplexer for data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If registers are used to implement small-capacity memory design, then memory capacity flexibility is improved, but logic resource consumption increases significantly
Solution Approach 1:
The invention divides the memory system into multiple local storage units (LSUs), each capable of independent configuration. Each LSU can be configured as different memory depths (e.g., 8-depth or 4-depth), allowing flexible combination to achieve various total capacities without requiring excessive logic resources for address control
Solution Approach 2:
The local storage units are designed with multi-functionality, where each LSU can operate in different configuration modes (8-depth memory mode, 4-depth memory mode, etc.). This universal design allows the same hardware structure to serve multiple memory capacity needs, reducing the requirement for additional logic resources
2Quantity of substance
If block memories are used to implement small-capacity memory design, then logic resource consumption is reduced, but storage resource wastage increases
Solution Approach 1:
The invention applies local quality by making each local storage unit independently configurable with specific memory depths. Instead of using fixed-size block memories that waste capacity, each LSU can be precisely configured to match the required storage capacity, eliminating storage resource wastage while maintaining low logic resource consumption
3Ease of manufacture
If fixed-capacity block memories are used, then storage resource utilization is simplified, but scalability and flexibility of storage performance deteriorate
Solution Approach 1:
The invention introduces dynamics by making the memory capacity configurable through control signals. The local storage units can dynamically switch between different operation modes (different memory depths) based on configuration inputs, providing both scalability and flexibility while maintaining simple resource utilization
Data Source
AI summary
An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.