Dual-Port SRAM Write Margin and Speed via Dynamic Pass-Gate Control
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Solution Overview
Problem
Dual-port SRAM circuits face instability during dual read operations due to double pass-gates causing high voltage on bit lines, leading to 'bit flip' issues and a trade-off between read and write margins, resulting in slow write speeds.
Innovation Solution
Implementing a controller that enables simultaneous use of two pass-gates per side for write operations, along with strength tuning of PFETs and NFETs to increase write margin and speed while maintaining acceptable read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two pass-gates are used on each side of the memory cell for dual-port operation, then read capability is improved, but write margin decreases and write speed becomes slow
Solution Approach 1:
The patent dynamically configures the pass-gate structure based on operation type: during write operations, only one pass-gate per side is enabled to maintain adequate write margin and speed, while during read operations, both pass-gates are enabled to achieve dual read capability. This dynamic switching resolves the contradiction by adapting the circuit configuration to the specific operation requirements.
Solution Approach 2:
The patent applies different operational characteristics to different sides of the memory cell locally. During write operations, the write port uses a single pass-gate configuration optimized for write margin, while the read port can utilize both pass-gates for read capability. This local differentiation allows each port to operate with optimal characteristics for its function.
2Reliability
If transistor strengths are optimized for read margin, then read stability is improved, but write margin decreases
Solution Approach 1:
The patent employs dynamic transistor strength configuration where the relative strengths of PFETs and NFETs are adjusted based on the operation mode. During read operations, transistor strengths are optimized for read margin to ensure read stability, while during write operations, the strengths are reconfigured to improve write margin. This dynamic adjustment resolves the trade-off between read and write margins.
Solution Approach 2:
The patent changes the electrical parameters (transistor strengths) of the memory cell based on operation type. By modifying the relative strengths of PFETs and NFETs dynamically, the circuit can achieve optimal read margin during read operations and optimal write margin during write operations, resolving the contradiction between these two parameters.
3Strength
If higher voltage is applied to bit lines during dual read, then read signal strength is improved, but cell stability decreases causing bit flips
Solution Approach 1:
The patent extracts or removes the harmful high voltage condition from the bit lines during write operations. By disabling one pass-gate per side during writes, the high voltage that causes disturbance and bit flips is eliminated, while maintaining sufficient read signal strength through the enabled pass-gate configuration.
Solution Approach 2:
The patent applies preliminary anti-action by preventing the harmful high voltage condition before it can cause bit flips. The controller proactively disables the unnecessary pass-gates before write operations begin, preventing the voltage disturbance that would otherwise destabilize the cell and cause incorrect bit values.
Data Source
AI summary
A multiple-port RAM circuit has a data-in line (DIN) coupled to multiple bit lines (a-bit, b-bit) and multiple bit line bars (a-bitb, b-bitb). The circuit also has multiple word lines (a-wl, b-wl). A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller (201) that enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.