Memory Error Detection Circuitry for Fast Soft Error Correction
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Solution Overview
Problem
Conventional error detection circuitry in programmable integrated circuits is slow in detecting and correcting soft errors caused by radiation, leading to frequent disruptions and power consumption issues due to the need to reload configuration data.
Innovation Solution
The integration of error detection circuitry with logic XOR gates arranged in linear chains or binary trees, allowing for rapid detection of single-bit or multi-bit errors, and the use of error correction circuitry to correct these errors, with the error detection circuitry being significantly faster than the correction circuitry to minimize disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sequential error detection circuitry is used, then the circuit complexity is relatively simple, but the error detection speed is slow requiring more than 100 million clock cycles
Solution Approach 1:
The patent divides the array of configuration memory cells into multiple groups, with each group processed by a separate error detection circuit. This segmentation allows parallel processing of multiple groups simultaneously, dramatically increasing error detection speed while keeping each individual detection circuit relatively simple.
Solution Approach 2:
The patent transitions from sequential single-bit error detection to parallel multi-bit error detection by organizing detection circuits to process multiple memory cells simultaneously. This dimensional change from time-sequential to space-parallel processing achieves over 100-fold speed improvement.
2Reliability
If the entire programmable device is reloaded every time a soft error is detected, then reliability is improved, but productivity decreases due to frequent disruptions and power consumption increases
Solution Approach 1:
The patent extracts and corrects only the specific erroneous configuration bits identified by the error detection circuit, rather than reloading the entire configuration memory. This selective correction approach maintains reliability by fixing errors while preserving productivity by avoiding unnecessary full reloads and associated power consumption.
Solution Approach 2:
The error correction circuit automatically corrects detected soft errors in configuration memory cells without requiring system intervention or complete reconfiguration. This self-correcting mechanism ensures continuous operation and maintains both reliability and productivity.
3Reliability
If configuration memory cells are redesigned to prevent soft errors, then reliability is improved, but device complexity increases and additional circuit real estate is consumed
Solution Approach 1:
The patent introduces separate error detection and correction circuits as intermediary components that work with the existing configuration memory cells. Rather than redesigning the memory cells themselves, these intermediary circuits monitor and correct errors, achieving improved reliability without increasing the complexity or real estate of the configuration memory structure.
Data Source
AI summary
Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.