Multi-Phase Clock Division for Reliable Strobe Phase Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor systems, the increasing operation rate leads to phase differences between operation signals applied to various operation units, causing reliability and stability issues during phase detection operations, especially due to signal integrity and reception buffer characteristics.
Innovation Solution
A semiconductor apparatus with a clock division block generating internal clocks with specific phase differences and a phase detection block combining detection results from these internal clocks and a strobe signal to improve phase synchronization, using a method that samples logic values at edges rather than comparing edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation rate of electronic apparatus is increased, then productivity is improved, but phase differences between operation signals occur causing reliability deterioration
Solution Approach 1:
The source clock phase is divided into multiple internal clock phases (first internal clock and second internal clock) using a clock division block. This segmentation allows the phase detection block to detect phase differences by comparing multiple divided phases against the strobe signal, improving detection reliability at high operation rates where single-phase detection would fail.
2Device complexity
If phase detection is performed by comparing edges directly, then device complexity is reduced, but measurement precision deteriorates due to phase reversals
Solution Approach 1:
Instead of comparing edges directly in one dimension, the invention samples logic values at specific edges and processes them through multiple clock phases. This adds temporal dimensionality to the detection process, allowing accurate phase difference measurement even when phase reversals occur, without significantly increasing device complexity.
Data Source
AI summary
A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.