DDR Latch Ring Counter for Compact CMOS Image Sensor Decoding
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Solution Overview
Problem
Conventional CMOS image sensors require a large size to accommodate multiple address lines and lack a latch-based decoding device capable of operating at a double data rate to facilitate effective channel selection with a single address.
Innovation Solution
A latch circuit and double data rate decoding device are implemented using a feedback input unit and latching unit that operate at a shifting clock, with alternating positive-edge-triggered and negative-edge-triggered latches to enable double data rate operation, reducing the need for address lines and allowing channel selection at each clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional address decoding schemes are used, then multiple address lines are required to select desired lines, but the size of the CMOS image sensor must be sufficiently large to accommodate the address lines
Solution Approach 1:
The address decoding function is segmented into multiple latch stages (first latch stage, second latch stage, third latch stage) that operate sequentially. Each latch stage processes a portion of the address decoding task, allowing the system to achieve full decoding capability with fewer physical address lines while maintaining the same channel selection functionality.
Solution Approach 2:
The latch circuit operates in periodic cycles, alternating between latching states and transfer states. During each period, the latch stages sequentially capture and transfer address signals, enabling the system to process address information over time rather than requiring all address lines to be simultaneously present, thereby reducing the spatial requirement.
2Productivity
If a latch-based decoding device operates at single data rate, then channel selection is limited, but operating at double data rate requires complex timing control
Solution Approach 1:
The double data rate operation is achieved by segmenting the latch circuit into multiple independent latch stages (first, second, and third latch stages) with alternating positive-edge and negative-edge triggering. Each latch stage handles specific timing requirements independently, simplifying the overall timing control while achieving double data rate throughput.
Solution Approach 2:
The latch stages alternate between positive-edge-triggered and negative-edge-triggered configurations. This inversion approach allows the circuit to capture data on both rising and falling edges of the clock signal, effectively doubling the data processing rate without requiring complex multi-phase clocking schemes.
Data Source
AI summary
Disclosed are a latch circuit receiving a negative output of a next latch stage circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a form of a ring. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current latch stage receives an output of a preceding latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.