Memory CRC Training Circuit for Faster Read and Write Alignment
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Solution Overview
Problem
Current semiconductor memory apparatuses face challenges in efficiently performing training operations to ensure data integrity and synchronization between controllers and memory devices, particularly in generating and comparing cyclic redundancy check (CRC) information for effective data storage and retrieval.
Innovation Solution
Incorporation of a CRC circuit block, training determination block, write pipe latch block, and read pipe latch control block within the semiconductor memory apparatus to generate internal CRC information, compare it with external information, and control data latching and output operations based on training signals, thereby enabling efficient read and write training operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional training operations are used in semiconductor memory apparatuses, then data integrity can be maintained through CRC checking, but the training process time is excessively long and efficiency is low
Solution Approach 1:
The patent applies preliminary action by pre-configuring dual pipe latch blocks (first and second pipe latch blocks) to simultaneously latch data during the training operation. This allows the memory apparatus to prepare multiple data paths in advance, enabling parallel processing of training data and significantly reducing the overall training time while maintaining data integrity through concurrent CRC verification.
Solution Approach 2:
The patent segments the training operation into parallel paths by dividing the data latching function into multiple independent pipe latch blocks. Each latch block processes data independently through its own data path, allowing simultaneous execution of multiple training operations. This segmentation enables the system to verify data integrity through multiple parallel CRC checks rather than sequential verification.
2Productivity
If multiple data paths are used for parallel training operations, then training efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing the second pipe latch block and second data path to perform the same functions as the first pipe latch block and first data path. Both latch blocks are configured identically to handle data latching, and both paths include CRC verification capability. This multi-functional design allows the system to achieve parallel processing without requiring fundamentally different circuit architectures, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent applies copying by creating a duplicate of the first data path and first pipe latch block to form the second data path and second pipe latch block. This replicated structure enables parallel training operations by maintaining identical functional units that can operate simultaneously. The copying approach ensures that the additional complexity is minimal, as the second path is essentially a duplicate of the first, rather than requiring entirely new circuit designs.
Data Source
AI summary
A semiconductor memory apparatus may include a cyclic redundancy check (CRC) circuit block electrically coupled with a first pad, and configured to generate internal CRC information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external CRC information received from outside the semiconductor memory apparatus with the internal CRC information, and generate a read training result signal.