Memory Refresh Circuit for Reed-Solomon ECC SEU Correction
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Solution Overview
Problem
Large Reed-Solomon ECC circuitry with parallel memories faces challenges in error correction due to uncorrected single event upsets (SEUs), where error correction circuitry can be as costly as the rest of the circuitry, and existing memory refresh methods are unreliable over long periods.
Innovation Solution
A method and circuitry for refreshing memory in Reed-Solomon ECC systems using an algorithmic data generation circuit that generates write addresses and corrected data, employing Galois Field multipliers and registers to correct errors by overwriting original data, and utilizing a true dual-port memory for efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large parallel memories are used in Reed-Solomon ECC circuitry, then memory capacity is improved, but error correction capability deteriorates because SEUs remain uncorrected and error correction circuitry cost increases significantly
Solution Approach 1:
The patent applies preliminary action by periodically refreshing memory contents before errors can accumulate to problematic levels. The memory refresh circuit systematically iterates through all memory locations and reconstructs data using Reed-Solomon error correction algorithms, preventing single event upsets from degrading reliability in large capacity memories
Solution Approach 2:
The patent introduces a memory refresh circuit as an intermediary component that mediates between the large parallel memories and the error correction requirements. This refresh circuit acts as a buffer, periodically correcting errors in the memory contents without requiring the main Reed-Solomon ECC circuitry to be constantly active, thus maintaining reliability while preserving memory capacity
2Reliability
If extensive error correction circuitry is added to correct SEUs, then reliability is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent applies periodic action by implementing a memory refresh circuit that operates at regular intervals rather than continuously. The refresh circuit systematically iterates through memory locations periodically, correcting errors before they affect system operation. This periodic approach maintains reliability while avoiding the continuous complexity and cost of extensive real-time error correction circuitry
Solution Approach 2:
The memory refresh circuit enables the memory system to self-correct errors without requiring external intervention or complex continuous monitoring. By periodically reconstructing and rewriting correct data to memory locations, the system serves its own error correction needs, reducing the burden on additional error correction circuitry
3Ease of manufacture
If traditional memory refresh methods are used, then implementation simplicity is maintained, but reliability deteriorates over long periods
Solution Approach 1:
The patent replaces traditional mechanical or simple refresh methods with an algorithmic data generation circuit that uses Galois Field multipliers and mathematical operations. Instead of simple data rewriting, the system generates corrected data through finite field arithmetic operations (GF multipliers multiplying field elements), providing robust long-term reliability while maintaining implementation feasibility through structured algorithmic approaches
Data Source
AI summary
A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation circuit that generates write addresses and correct data such that the correct data is stored in the memory circuit at locations that are indicated by the write addresses to correct errors in the original data by overwriting the original data with the correct data during a random access mode of operation of the memory circuit.