FeRAM Cell Structure for Non-Destructive Readout

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Solution Overview

Problem

In Ferroelectric Random Access Memory (FeRAM) with 1T1C or 1TXC architecture, the reading operation is destructive, requiring a writing-back operation that can destroy the memory state, necessitating a non-destructive reading method.

Innovation Solution

A semiconductor device design where a first select transistor and a second select transistor are connected to a capacitor structure, with the two ends of the first electrode layer connected to the first channel layer of the first select transistor and the gate of the second select transistor, allowing the transistors to perform writing and reading operations respectively, eliminating the need for a writing-back operation and enabling non-destructive reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a 1T1C or 1TXC architecture is used in FeRAM, then the device structure is simple and manufacturing is easier, but the reading operation becomes destructive and requires additional writing-back operations

Engineering Contradiction:
Improvedevice structureVSAvoidreading operation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The invention divides the single transistor into two separate select transistors (first select transistor and second select transistor), each with distinct functions. The first select transistor controls writing operations while the second select transistor controls reading operations. This segmentation allows the reading operation to be non-destructive by properly controlling the state of the capacitor during read, eliminating the need for writing-back operations while maintaining manufacturing simplicity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The capacitor structure in the invention serves multiple functions: it stores data states (representing binary 0 or 1 through different resistance states), acts as a memory element that maintains its state during operations, and enables both read and write operations without destruction. The dual-transistor configuration allows the same capacitor to be used for both reading and writing with appropriate transistor control

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a writing-back operation is performed after reading in 1T1C FeRAM, then the memory state can be restored, but the operation time increases and efficiency decreases

Engineering Contradiction:
Improvememory stateVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention performs preliminary configuration of the transistor states and capacitor connections before the reading operation. The second select transistor is specifically designed and positioned to enable non-destructive reading from the outset. By properly initializing the circuit state and using the second select transistor to control the read path, the system avoids the need for subsequent writing-back operations, thus saving time while maintaining memory state integrity

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the first electrode layer is connected to both the first channel layer and the gate, then non-destructive reading is enabled, but the device structure becomes more complex

Engineering Contradiction:
Improvereading operationVSAvoidconnection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first electrode layer acts as an intermediary element that connects both the first channel layer and the gate of the second select transistor. This intermediary structure allows the capacitor to be controlled by the gate while also being accessible through the first channel layer. The dual connection enables the capacitor to function as both a storage element and a controlled component, facilitating non-destructive reading operations

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240407174A1Semiconductor devices and fabrication methods thereof and memory systems
Publication Date: 2024.12.05 YANGTZE MEMORY TECH CO LTD
  • US20240407174A1 patent drawing
  • US20240407174A1 patent drawing
  • US20240407174A1 patent drawing

AI summary

The present application provides a semiconductor device and a fabrication method thereof, and a memory system. The semiconductor structure includes a first semiconductor structure which includes: a first select transistor including a first channel layer; a second select transistor including a gate; and a capacitor structure including a first electrode layer, wherein two ends of the first electrode layer are connected with the gate of the second select transistor and the first channel layer of the first select transistor respectively. The present application can avoid the problem of state destruction caused by reading operation.