Freeze-Test Memory Circuit for Soft-Error-Resistant PLD Configuration
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Solution Overview
Problem
Programmable logic devices (PLDs) face issues with soft error upsets and volatility in configuration RAM (CRAM), leading to increased component sizes and voltages, as well as performance degradation with smaller process nodes, which complicates scaling and introduces delays in readying the PLD.
Innovation Solution
A memory circuit comprising a first and second memory device, each capable of being programmed in a specific state, with a freeze circuit and test switch to manage and test the states, utilizing MEMS switching devices or conductive bridge devices to store one bit of data, allowing for non-volatile operation and reduced susceptibility to soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CRAM is implemented as SRAM to provide field programmability, then configuration flexibility is improved, but susceptibility to soft error upsets increases
Solution Approach 1:
The patent applies preliminary action by pre-programming configuration data into non-volatile memory cells before the PLD is operational. The configuration data is stored in a permanent form using conductive bridge or MEMS devices, eliminating the need for volatile CRAM and preventing soft errors from occurring during operation. This preliminary programming action resolves the contradiction by providing both configuration flexibility and soft error immunity simultaneously.
2Productivity
If component device sizes are reduced to increase integration density, then productivity is improved, but soft error rate increases
Solution Approach 1:
The patent applies parameter changes by transitioning from volatile SRAM-based configuration elements to non-volatile memory cells with different physical characteristics. The non-volatile memory cells use conductive bridge or MEMS devices that maintain their state without power and are inherently more resistant to soft errors. This parameter change in the memory technology enables smaller device sizes for higher integration density while simultaneously reducing soft error rates.
3Reliability
If larger component devices and higher voltages are used to reduce soft errors, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent applies mechanics substitution by replacing the traditional SRAM-based electrical memory system with a non-volatile memory system using conductive bridge or MEMS devices. These devices use different physical mechanisms (conductive filament formation or mechanical switching) that provide inherent soft error resistance without requiring larger device dimensions or higher operating voltages. This substitution resolves the contradiction by achieving reliability through mechanism change rather than scaling up physical parameters.
4Adaptability or versatility
If configuration data is loaded into CRAM at power-on to enable PLD operation, then adaptability is improved, but ready time increases
Solution Approach 1:
The patent applies preliminary action by pre-storing configuration data in non-volatile memory cells before the PLD is powered on. The configuration data remains permanently stored in the memory cells using conductive bridge or MEMS devices, eliminating the need for time-consuming data loading operations at power-on. This preliminary programming action resolves the contradiction by providing both configuration adaptability and immediate operational readiness.
Data Source
AI summary
In one aspect, a memory circuit is provided. The memory circuit includes a first memory device; a second memory device coupled to the first memory device; a freeze circuit coupled to a first output terminal and a second output terminal, where the first output terminal is an output terminal of the first memory device and the second output terminal is an output terminal of the second memory device; and a test switch coupled to the first output terminal and the second output terminal.