Ferroelectric Capacitor Sidewall Dielectric to Prevent Electrode Shorting
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Solution Overview
Problem
Current memory technologies, such as SRAM and DRAM, are volatile and not suitable for low power and compact computing due to high write energy, low density, and high power consumption, while non-volatile memories like MRAM and flash memories face challenges in advanced technology nodes like 7 nm and below, where electrode shorting during fabrication is a significant issue.
Innovation Solution
A method for forming a ferroelectric capacitor that involves depositing a stack of layers with conductive electrodes and a ferroelectric material, followed by etching and conformably depositing a non-conductive dielectric to prevent shorting, and forming a metal cap to protect the dielectric, allowing for the creation of a non-volatile memory bit-cell that can operate at low voltages and high density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memory is used to replace magnetic hard disks, then data retention is improved, but write energy and power consumption increase
Solution Approach 1:
The patent changes the material parameter by using ferroelectric material instead of traditional magnetic or charge-based storage, enabling non-volatile storage with lower write energy through electric field-induced polarization switching
Solution Approach 2:
The patent employs composite material structure with ferroelectric layer combined with electrode materials (such as Pt, IrO2, or RuO2) to achieve both non-volatile data retention and low power consumption through the unique properties of ferroelectric compounds
2Quantity of substance
If electrode dimensions are reduced for high density, then storage density is improved, but electrode shorting during fabrication increases
Solution Approach 1:
The patent introduces a ferroelectric layer as an intermediary between the top and bottom electrodes, which serves as both the storage medium and an insulating barrier that prevents electrode shorting during fabrication and operation, enabling continued scaling to higher densities
Solution Approach 2:
The patent transitions from planar electrode structures to vertically stacked three-dimensional structures with the ferroelectric layer positioned between electrodes in the vertical dimension, increasing storage density while maintaining adequate spacing to prevent shorting
3Ease of manufacture
If conventional memory structures are used, then manufacturing process is simple, but power consumption and area are high
Solution Approach 1:
The patent merges the memory storage function with logic device functionality by integrating ferroelectric capacitors directly into the logic device structure, eliminating separate memory components and reducing overall power consumption and chip area while maintaining compatibility with conventional semiconductor manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures that ferroelectric capacitors are fabricated without electrode shorting, enabling the creation of non-volatile memory bit-cells that can operate at low voltages and achieve higher density, addressing the limitations of traditional DRAMs and advanced technology node challenges.
Implementation Method 1
a structure with ferroelectric material
Implementation Method 2
a dielectric adjacent to sidewalls of at least the first and second electrodes
Data Source
AI summary
Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.