Correlated Electron Switch FPGA Routing Without External Memory
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Solution Overview
Problem
Conventional Field Programmable Gate Array (FPGA) devices rely on external memory for switch configuration, which occupies physical space and limits scalability, especially below 40 nanometers, as they require additional memory devices to store switch states.
Innovation Solution
The integration of Correlated Electron Switches (CES) within the FPGA architecture, which are non-volatile and can be programmed to enable or disable connections between logic circuits, eliminating the need for external memory by maintaining impedance states even without a voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external memory is used to store switch configuration, then switch state can be maintained, but device size increases and scalability is limited
Solution Approach 1:
The patent merges the external memory function with the switch block by integrating non-volatile memory elements directly into the switch block architecture. This allows the switch configuration to be stored locally within the FPGA device, eliminating the need for separate external memory components while maintaining switch state reliability.
Solution Approach 2:
The patent extracts the memory function from external components and relocates it into the switch block itself. By embedding non-volatile memory elements within the switch block, the configuration data is stored locally, removing the dependency on external memory and reducing overall device volume.
2Adaptability or versatility
If external memory devices are integrated, then configuration storage is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions (switching and memory storage) into a single integrated switch block structure. This consolidation reduces the number of discrete components and interconnections required, thereby simplifying the manufacturing process while maintaining configuration storage capability.
Solution Approach 2:
The switch block is designed to perform multiple functions: it acts as both a switching element and a memory storage unit. This multi-functionality eliminates the need for separate dedicated memory devices, reducing manufacturing complexity while preserving configuration storage adaptability.
3Ease of operation
If switch blocks use conventional switches with external memory, then routing functionality is achieved, but physical space is occupied
Solution Approach 1:
The patent implements a nested structure where non-volatile memory elements are embedded within the switch block architecture. This nesting allows the memory function to be housed within the existing switch block footprint, maintaining routing functionality while minimizing additional physical space requirements.
Solution Approach 2:
By merging the memory storage function with the switch block structure, the patent eliminates the need for separate external memory components. This integration maintains full routing functionality while significantly reducing the physical area occupied by configuration storage elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the physical size of FPGA devices by eliminating the need for external memory, allowing for more compact designs and improved scalability, while enabling efficient signal routing through programmable impedance states.
Implementation Method 1
The CES element may be programmed into a first impedance state or a second impedance state. The first impedance state may be a low impedance state and the second impedance state may be a high impedance state.
Data Source
AI summary
Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.