Self-Reset Clock Buffer Using Feedback for Low-Voltage Memory Timing
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Solution Overview
Problem
Conventional clock buffers in memory devices face issues such as reliance on hard delays leading to timing violations, increased circuit area due to multiple transistors, high load on external clock signals, and failure at lower supply voltages due to contention between clock generator and keeper circuit.
Innovation Solution
The proposed clock buffer incorporates self-reset functionality using cross-coupled logic circuitry, reducing the need for delay circuits and nFETs, and replacing latch circuitry with a tri-state inverter to maintain signal integrity across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is used to ensure the output clock is pulled down before pull down is disabled, then the clock generator reliability is improved, but timing violations occur and the hold time increases
Solution Approach 1:
The patent uses feedback from the output clock signal to control the pull-down transistor. The output clock signal directly controls when the pull-down path is disabled, eliminating the need for a separate delay circuit. This feedback mechanism ensures the output is properly pulled down while minimizing the hold time requirement.
Solution Approach 2:
The circuit uses its own output clock signal to control its own pull-down timing. The output clock signal feeds back to disable the pull-down transistor, making the circuit self-regulating and eliminating external delay requirements.
2Reliability
If two nFET transistors are used in the pull-down circuit to combine clock signals, then the logic function is achieved, but the circuit area increases and storage density decreases
Solution Approach 1:
The patent removes one of the two nFET transistors from the conventional design. By using feedback control, the circuit achieves the same logic function with only one nFET in the pull-down path, reducing circuit area while maintaining functionality.
Solution Approach 2:
The patent introduces the output clock signal as an intermediary to control the pull-down transistor gate. This intermediary signal enables the single nFET to perform the logic function that previously required two transistors, reducing area while maintaining correctness.
3Reliability
If two nFET transistors are used in the pull-down circuit, then the logic function is achieved, but the capacitance increases the load on the external clock
Solution Approach 1:
The patent removes one nFET from the pull-down circuit, directly reducing the total capacitance that the external clock must drive. This extraction of the redundant transistor reduces the load on the external clock signal while maintaining the necessary logic function through feedback control.
4Reliability
If conventional latch circuitry is used in the keeper circuit, then the clock buffer operates at higher supply voltages, but the clock generator fails at lower supply voltages due to contention
Solution Approach 1:
The patent replaces the static latch circuitry with a dynamic tri-state inverter controlled by the reset signal and output clock signal. This dynamic approach allows the keeper circuit to be selectively enabled or disabled, preventing contention with the clock generator at low supply voltages while maintaining functionality when needed.
Solution Approach 2:
The patent changes the operational parameters of the keeper circuit by using a tri-state inverter instead of a latch. The tri-state configuration allows the keeper to be in high-impedance mode during certain phases, changing the electrical parameters to prevent contention and enable operation at lower supply voltages.
5Reliability
If the chip select line is held low for the duration of the clock delay, then the clock buffer operates correctly, but the setup time for memory latches is reduced
Solution Approach 1:
The patent uses feedback from the output clock signal to control the pull-down transistor timing. This feedback mechanism synchronizes the pull-down disable timing with the actual output clock edge, eliminating the need for excessive hold time and maximizing the setup time available for memory latches.
Data Source
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AI summary
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.