Row-Wise Gated Memory Circuitry for Low-Voltage Write Margins
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Solution Overview
Problem
As semiconductor technology scales towards smaller dimensions and lower power supply voltages, volatile memory elements in integrated circuits face decreased read and write margins, posing challenges for reliable device operation.
Innovation Solution
The implementation of a row-wise gated 8T register file with power supply gating circuitry that provides a gated power supply voltage to memory cells, allowing the power supply to be tri-stated or driven to ground during write operations, thereby reducing the pull-up current path and improving write margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If lower power supply voltages are used to reduce power consumption, then energy efficiency improves, but write margins decrease
Solution Approach 1:
The power supply to memory cells is segmented into row-specific segments through power supply gating circuitry. Each row can have its power supply independently controlled, allowing write operations to be performed on selected rows while maintaining stable power supply to other rows. This segmentation enables improved write margins for active rows without increasing overall power consumption across the entire memory array.
Solution Approach 2:
The patent dynamically changes the power supply parameter for memory cells based on operational mode. During write operations, the power supply voltage to selected rows is adjusted (gated) to optimize write margins, while during normal operation, the standard lower power supply voltage is maintained for energy efficiency. This parameter change allows the system to adapt to different operational requirements.
2Speed
If conventional write operations are performed with continuous power supply, then write speed is maintained, but drive conflict between pull-up and write access transistors reduces write margins
Solution Approach 1:
The power supply gating circuitry is activated in advance of the write operation to prepare the memory cell power supply state. By preemptively gating the power supply to selected rows before the write operation begins, the circuit eliminates the drive conflict condition that would otherwise occur between the pull-up transistors and write access transistors during the write operation, thereby improving write margins without compromising write speed.
3Reliability
If power supply gating is implemented on a per-row basis, then write margins are improved, but device complexity increases
Solution Approach 1:
The power supply gating circuitry is designed to serve multiple functions: it enables row-specific power control for improved write margins, maintains data retention in non-selected rows, and can be controlled through existing control signals. This multi-functionality reduces the need for additional dedicated circuitry and minimizes overall device complexity while achieving the desired write margin improvement.
Data Source
AI summary
An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are connected to shared word lines. The memory cells in the same row may also be connected to a row control line. During normal operations, the row control line may provide a positive power supply voltage to each memory cell along that row. During write operations, the row control line may be driven to ground or tri-stated to help improve the write margin and the write performance of the selected memory cells. The aspect ratio of these memory cells may also be more square-like or balanced to help improve power delivery.