FeFET NAND Memory Cell Layout for Read Margin and IR Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional NAND-type memory using ferroelectric field effect transistors (FeFETs) faces issues with small read margin due to high variability in ferroelectric material grain/domains and high IR drop, leading to low read/program speed.
Innovation Solution
The implementation of a memory device with a ferroelectric field effect transistor (FeFET) and a second transistor sharing gate, source, and drain terminals, along with a ferroelectric capacitor, enhances current flow and access speed by enlarging the current through memory cells, thereby improving read and write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If traditional NAND-type memory uses FeFETs, then non-volatile storage is achieved, but read margin becomes small due to high variability from ferroelectric material grain/domains
Solution Approach 1:
The patent merges two transistors into a single memory cell structure where a first FeFET and a second transistor share common gate, source, and drain terminals. This combined configuration allows the first FeFET to provide non-volatile storage while the second transistor compensates for variability issues, thereby maintaining non-volatility while improving read margin and reducing IR drop effects.
2Productivity
If traditional NAND-type memory uses FeFETs, then memory functionality is achieved, but IR drop becomes very high causing low read/program speed
Solution Approach 1:
By combining two transistors with shared terminals, the patent creates a configuration where the second transistor provides an additional current path that compensates for the high IR drop in traditional single-transistor FeFET memory. This merging approach maintains full memory functionality while significantly improving read and program speeds by reducing the impact of resistive voltage drops.
Data Source
AI summary
A method includes: providing a substrate including a planar portion and a mesa portion over the planar portion; depositing an oxide layer over the mesa portion; depositing a ferroelectric material strip over the oxide layer and aligned with the mesa portion; and depositing a gate strip crossing the ferroelectric material strip and over the oxide layer.