Oxide Semiconductor Memory Cell Layout for Lower Bitline Capacitance
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Solution Overview
Problem
Memory devices with silicon semiconductors experience significant parasitic capacitance between source/drain regions and the semiconductor substrate, leading to increased leakage current and decreased retention time, which in turn affects operating speed and power consumption.
Innovation Solution
The use of oxide semiconductors in memory devices, specifically in access transistors and capacitors, reduces parasitic capacitance by minimizing leakage current and enhancing retention time through the implementation of a bitline and complementary bitline configuration with precharge and sense amplification circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are implemented with silicon semiconductors, then the memory device can achieve basic transistor functionality, but parasitic capacitance between source/drain regions and substrate increases, leading to increased bitline capacitance
Solution Approach 1:
The patent changes the material parameter from silicon semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics. This material substitution reduces parasitic capacitance between source/drain regions and substrate while maintaining transistor functionality, directly resolving the technical contradiction
Solution Approach 2:
The patent employs oxide semiconductor materials as a composite solution that combines the desired transistor functionality with reduced parasitic capacitance characteristics. The oxide semiconductor layer works in conjunction with other device components to achieve both functional reliability and reduced harmful capacitance effects
2Speed
If voltage difference between source and drain increases, then transistor switching capability improves, but leakage current increases, causing decreased retention time
Solution Approach 1:
The patent changes the semiconductor material parameter to oxide semiconductor, which has fundamentally different electrical properties including lower leakage current characteristics. This allows the device to maintain effective switching capability while significantly reducing leakage current, thereby resolving the contradiction between switching speed and energy loss
3Speed
If retention time decreases, then memory device can operate faster, but power consumption increases
Solution Approach 1:
By changing the material parameter to oxide semiconductor, the patent achieves a device that maintains data retention for longer periods without requiring excessive refresh operations. This reduces the overall power consumption while maintaining operational speed, as the lower leakage current characteristic allows for slower refresh cycles
Data Source
AI summary
A memory device includes a first memory cell connected to a first bitline and a second memory cell connected to a second bitline, wherein the first memory cell may include a first access transistor including one end connected to the first bitline, and a first capacitor including one electrode connected to another end of the first access transistor and another electrode connected to the second bitline, and the first access transistor may include an oxide semiconductor.