Z2-FET Memory Cell Layout for Precise Narrow-Gate Contacts
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Solution Overview
Problem
Current memory circuits face challenges in miniaturization due to limitations in mask accuracy and spacing, which hinder the formation of smaller Z2-FET-type structures and prevent the creation of contacts on insulated gates with narrow widths, such as 28 nm, leading to inefficiencies in manufacturing.
Innovation Solution
The implementation of a Z2-FET-type memory cell structure with two front gates separated by an insulating spacer, where the distance between the gates is less than 40% of their width, and the inclusion of two back gates with different doping types, allowing for improved control over charge flow and enabling the simultaneous formation of contacts without the need for additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between two front gates is reduced to enable miniaturization, then the memory circuit size is reduced, but mask accuracy and spacing limitations prevent precise contact formation on insulated gates with narrow widths
Solution Approach 1:
An insulating spacer is introduced as an intermediary element between the two front gates. This spacer serves as a physical mediator that defines the spacing between gates while allowing contact holes to be formed through the spacer material itself, bypassing the mask accuracy limitations that would otherwise prevent precise contact formation on narrowly spaced insulated gates
Solution Approach 2:
The structure is segmented into distinct functional regions: the insulating spacer is separated from the gate electrodes, and contact holes are formed independently through the spacer. This segmentation allows the contact formation process to be decoupled from the gate spacing constraints, enabling precise contact alignment even when gates are closely spaced
2Manufacturing precision
If additional masks are used to form contacts on insulated gates, then contact precision is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The insulating spacer serves multiple functions simultaneously: it provides electrical insulation between gates, defines the physical spacing between gates, and acts as the target layer for contact hole formation. By merging these functions into a single element, the need for additional masks to define contact positions on separately formed insulated gates is eliminated
Solution Approach 2:
The insulating spacer is designed to be self-aligned with the gate structures, and contact holes are formed directly through the spacer material itself. This self-service approach allows the spacer to automatically define the contact positions without requiring external mask alignment, thereby simplifying the manufacturing process while maintaining precision
Data Source
AI summary
A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.