DRAM Cell Access Architecture With Secondary Digit-Line Switching
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Solution Overview
Problem
Conventional DRAM architectures access all memory cells along a row when a wordline is activated, making it difficult to selectively access specific memory cells or individual cells, leading to inefficiencies in power consumption and data handling.
Innovation Solution
The integration of secondary access devices between primary access devices and digit lines allows for selective coupling of digit lines to specific memory cells along an activated row, enabling controlled access to individual memory cells by switching both primary and secondary access devices to their ON modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional DRAM architectures access all memory cells along a row when a wordline is activated, then complete row access is achieved, but power consumption increases and selective access capability is lost
Solution Approach 1:
The patent divides the access path into two segments: primary access devices (first transistors) that connect memory cells to digit lines, and secondary access devices (second transistors) that connect digit lines to sense amplifiers. This segmentation enables selective activation - only the specific memory cell requiring access has both its primary and secondary access devices turned ON, while all other access devices remain OFF, thereby reducing power consumption compared to activating entire rows.
2Ease of operation
If secondary access devices are added between primary access devices and digit lines, then selective memory cell access is enabled, but device complexity increases
Solution Approach 1:
The access path is segmented into primary access devices connected to memory cells and secondary access devices connected to sense amplifiers. This segmentation allows independent control - the primary access device selects which memory cell is accessed, while the secondary access device controls whether data is transferred to the sense amplifier. The segmented architecture achieves selective access without requiring complex control logic within each memory cell.
Solution Approach 2:
The secondary access device acts as an intermediary between the digit line and the sense amplifier. It controls the flow of data from the memory cell through the digit line to the sense amplifier, enabling selective access by acting as a gatekeeper. This intermediary approach simplifies the memory cell structure compared to integrating complex selection logic directly into the memory cell.
3Speed
If all memory cells along a row are accessed simultaneously, then data access speed is maintained, but unnecessary data handling increases power consumption
Solution Approach 1:
Instead of activating all primary and secondary access devices along a row (excessive action), the patent enables only the specific primary access device and its corresponding secondary access device that are needed for the particular memory cell access (partial action). This partial activation maintains the speed required for the accessed cell while avoiding the power consumption associated with activating unnecessary access devices and handling unwanted data.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for reduced power consumption and efficient data access by enabling selective memory cell access, allowing a common sense amplifier to be shared among multiple digit lines and reducing unnecessary data dumping, thereby improving the overall performance of DRAM architectures.
Implementation Method 1
The secondary access devices may be utilized to selectively couple the digit lines to only specific memory cells along an activated row
Implementation Method 2
an electrical field generated by voltage along the wordline may gatedly couple the bitline to the capacitor during read/write operations
Data Source
AI summary
Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.