Pipe Latch Signal Balancing for Reliable Semiconductor Operation

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Solution Overview

Problem

Semiconductor apparatuses face challenges in maintaining reliable operation due to discrepancies between the number of enabled pipe input and output signals, which can arise from factors like temperature variations, voltage fluctuations, and noise, leading to abnormal operations.

Innovation Solution

Incorporating a pipe input/output signal generation block, a pipe latch group, and an error detection block that generate and manage pipe input/output signals and error detection signals based on enable and end signals, ensuring equal numbers of enabled input and output signals through initialization upon error detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pipe latch circuits are used to process large amounts of information at high speed, then productivity is improved, but reliability deteriorates due to discrepancies between enabled input and output signals

Engineering Contradiction:
Improveinformation processing speedVSAvoidsignal transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the controller counts the number of enabled pipe input signals and pipe output signals, compares these counts, and generates an error detection signal when they differ. This feedback loop continuously monitors and corrects signal transmission discrepancies, ensuring reliability while maintaining high-speed operation through the pipe latch circuit.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The controller acts as an intermediary between the pipe latch circuit and the error detection mechanism. It receives signals from the pipe latch circuit, processes the signal counts, and generates control signals to correct any discrepancies. This intermediary function coordinates the high-speed data flow while ensuring signal integrity through systematic verification.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the number of pipe input and output signals is not equal, then abnormal operations occur, but adding error detection and correction mechanisms increases device complexity

Engineering Contradiction:
Improveoperation normalityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The controller performs multiple functions: it generates pipe input and output signals, counts enabled signals, compares signal counts, and generates error detection signals. By consolidating these functions into a single controller unit, the patent avoids the need for separate dedicated circuits for each function, thereby maintaining reliability while minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent monitors changes in signal parameters (the number of enabled input and output signals) and triggers error detection when parameter discrepancies occur. This parameter-based monitoring approach provides reliable error detection without requiring complex structural modifications, as it relies on counting and comparing signal states rather than additional hardware components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9660617B2Semiconductor apparatus
Publication Date: 2017.05.23 SK HYNIX INC
  • US9660617B2 patent drawing
  • US9660617B2 patent drawing
  • US9660617B2 patent drawing

AI summary

A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.