Vertical Gated Ferroelectric Memory Cells for Higher Array Density
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Solution Overview
Problem
Existing memory technologies, such as resistive random-access memories, magneto-resistive random-access memories, and ferroelectric random-access memories, face limitations in scaling down and increasing memory cell density due to size constraints of complementary metal-oxide-semiconductor (CMOS) transistors.
Innovation Solution
The development of gated ferroelectric memory devices formed in the back-end-of-line (BEOL) using a vertical field-controlled current selector switch and ferroelectric dielectric layers, which enhance memory cell density by leveraging smaller area requirements and improved gate control with gate-all-around electrode structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional CMOS transistors are used in memory cells, then the memory device can be manufactured with standard processes, but the memory cell density is limited due to the size constraints of CMOS transistors
Solution Approach 1:
The patent transitions from planar 2D memory cell layouts to vertical 3D stacked architectures. Memory cells are stacked vertically across multiple layers with word lines, bit lines, and select gates extending through the stack, enabling significantly higher density by utilizing the third dimension while maintaining compatibility with standard semiconductor manufacturing processes
Solution Approach 2:
The patent implements nested gate structures where select gates are positioned within and around memory cell transistors. The select gate is formed between the source/drain regions and wrapped around portions of the memory cell transistor channel, allowing multiple functional elements to occupy overlapping spatial regions and increase effective density
2Quantity of substance
If memory cell size is reduced to increase density, then more cells fit in the same area, but gate control over the channel becomes insufficient
Solution Approach 1:
The patent employs composite gate structures combining multiple materials with different properties. The select gate uses a first conductive material while memory cell gates use a second conductive material, allowing optimization of each gate's electrical characteristics. High-k dielectric materials are also used in gate insulators to enhance control efficiency
Solution Approach 2:
The select gate is formed with a wrapped or curved configuration that surrounds portions of the memory cell transistor channel. This curved geometry provides enhanced electrostatic control over the channel compared to linear gate structures, improving reliability in compact cells
3Quantity of substance
If vertical stacked memory structures are implemented, then memory cell density increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating modular units stacked vertically. Each layer contains standardized components (memory cell transistors, word lines, bit lines, select gates) that can be manufactured using repeated process cycles, simplifying the overall manufacturing approach despite the vertical complexity
Solution Approach 2:
The patent designs universal gate structures that serve multiple functions. Select gates simultaneously provide channel formation, current selection, and electrical connection between layers. Word lines and bit lines serve both as signal conduits and as structural elements defining the memory cell array, reducing the number of separate manufacturing steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory cell density and improves gate control, enabling more compact and efficient memory devices with enhanced performance compared to conventional configurations.
Implementation Method 1
A ferroelectric material refers to a material that can maintain electrical polarization in the absence of external electrical field. The electrical polarization in a ferroelectric material has a hysteresis effect
Implementation Method 2
The electrical polarization in a ferroelectric material has a hysteresis effect, enabling encoding of a data bit as a polarization direction within the ferroelectric material
Implementation Method 3
In a ferroelectric tunnel junction device, a change in the direction of polarization causes a change in tunneling resistance, which can be employed to measure the direction of the electrical polarization and extract the value of the data bit stored in the ferroelectric tunnel junction
Data Source
AI summary
A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.