3D Memory Cell Structure With Recessed Dielectrics for Faster Writes
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Solution Overview
Problem
Current semiconductor memory technologies, such as volatile and non-volatile memories, face limitations in performance and efficiency, particularly in terms of write and read speeds, due to the use of planar channel regions in transistors, which restrict the development of high-density and high-performance memory devices.
Innovation Solution
The formation of three-dimensional channel regions in thin film transistors (TFTs) by recessing dielectric layers and depositing film stacks along the sidewalls and surfaces of word lines, allowing for improved transistor performance through increased electric field strength with lower gate voltages, and enhancing the efficiency of memory arrays by forming fin-like structures for word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If planar channel regions are used in transistors, then manufacturing is simpler, but write and read speeds are limited
Solution Approach 1:
The patent transitions from planar (2D) channel regions to three-dimensional channel regions by recessing dielectric layers and forming vertical fin-like structures. This dimensional change increases the effective channel area and electric field strength, enabling faster write and read speeds while maintaining manufacturing feasibility through established semiconductor processing techniques.
2Power
If three-dimensional channel regions are formed by recessing dielectric layers and depositing film stacks, then electric field strength increases with lower gate voltages, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary recessing of dielectric layers before depositing the film stacks for three-dimensional channel regions. This preliminary action creates the necessary geometric structure in advance, allowing subsequent deposition processes to form the desired fin-like configurations. This sequencing of operations manages manufacturing complexity by breaking down the complex three-dimensional formation into manageable sequential steps.
3Productivity
If fin-like structures are formed for word lines, then memory array efficiency is enhanced, but device size increases
Solution Approach 1:
The patent forms vertical fin-like structures for word lines that extend into the substrate, utilizing the vertical dimension to increase the effective word line length and memory array efficiency. This three-dimensional configuration allows for enhanced memory density and performance without proportionally increasing the planar footprint of the device, as the additional storage capacity is achieved through vertical extension rather than lateral expansion.
Data Source
AI summary
In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.