SoC Programmable Logic Accelerator With Banked FPGA Reconfiguration
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Solution Overview
Problem
Conventional Systems on Chips (SOC) with programmable logic accelerators face limitations in flexibility and performance due to resource constraints, particularly in integrating Field Programmable Gate Arrays (FPGAs) with SOC architecture, which hinders efficient use of operating system resources and leads to configuration load penalties during logic processing.
Innovation Solution
A Programmable Logic Accelerator (PLA) is integrated within SOC using Programmable Logic Tiles (PLT) connected via SOC interface bus and Logic Processing Block (LPB), featuring programmable logic cells, interface blocks, and configuration memory banks to enable seamless interaction with SOC components and avoid configuration load penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to provide programmable logic in SOC, then flexibility and logic configurability are improved, but area and power consumption increase
Solution Approach 1:
The FPGA fabric is segmented into multiple configuration memory banks (first configuration memory bank, second configuration memory bank) that can be independently managed. This segmentation allows parallel configuration operations and enables the system to switch between different logic configurations without reconfiguring the entire FPGA, thereby reducing the area required for configuration storage while maintaining logic configurability.
Solution Approach 2:
Configuration data is pre-loaded into configuration memory banks before logic processing begins. The system prepares multiple configuration sets in advance, allowing rapid switching between different logic functions without incurring configuration load penalties during runtime, thus maintaining flexibility while reducing the area needed for dynamic reconfiguration.
2Adaptability or versatility
If FPGAs are used to provide programmable logic in SOC, then logic configurability is improved, but power consumption increases
Solution Approach 1:
The configuration memory is divided into multiple banks that can be independently activated. Only the required configuration banks are powered and accessed at any given time, reducing overall power consumption while maintaining the ability to reconfigure logic functions as needed.
Solution Approach 2:
Configuration data is pre-loaded into memory banks during low-power states or idle periods. During active logic processing, the system switches between pre-configured banks without requiring energy-intensive reconfiguration operations, thereby reducing power consumption while preserving logic configurability.
3Adaptability or versatility
If configuration memory is used for logic processing in PLA, then configuration flexibility is improved, but configuration load penalty occurs during logic processing
Solution Approach 1:
Configuration memory is segmented into multiple banks that can be independently accessed and configured. While one bank is being used for active logic processing, another bank can be configured in parallel without blocking the processing pipeline, thereby eliminating configuration load penalties while maintaining configuration flexibility.
Solution Approach 2:
The system maintains continuous logic processing by switching between multiple configuration memory banks. While logic is being processed using one bank, configuration operations proceed in parallel on another bank, ensuring that useful action (logic processing) continues without interruption or penalty from configuration activities.
4Productivity
If PLA integrates with SOC architecture, then resource utilization efficiency is improved, but device complexity increases
Solution Approach 1:
The PLA is designed with universal interfaces and control mechanisms that allow it to function as multiple different logic configurations within the SOC architecture. By using standardized configuration memory banks and interface blocks, the PLA can adapt to various SOC components and protocols, improving resource utilization while managing integration complexity through multi-functionality rather than dedicated specialized interfaces.
Data Source
AI summary
A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.