MRAM Stack Structure for High TMR Without PMA Loss
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Solution Overview
Problem
Magnetic random access memory (MRAM) devices face limitations due to low tunneling magnetoresistance ratio (TMR) and resistance area product (RA) in existing stacks, which hinder their application and lead to read errors and reduced write/erase margins, and high thermal budgets during fabrication can further degrade the magnetic anisotropy and layer properties.
Innovation Solution
A stack design for MRAM devices with a top-pinned structure featuring in-plane textures for the substrate, electrode, seed metal, and tunnel barrier layers, along with a crystalline tunnel barrier layer and a synthetic antiferromagnetic pinning layer, allowing for improved TMR through enhanced crystallinity and thermal stability, achieved by decoupling thermal budgets during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high thermal budget is applied during fabrication to improve crystallinity of the tunnel barrier layer, then the TMR can be increased, but the perpendicular magnetic anisotropy (PMA) is lost and metal elements diffuse through the stack
Solution Approach 1:
The patent applies a preliminary low-temperature annealing treatment (200-400°C) to the tunnel barrier layer before depositing the magnetic layers. This preliminary action improves the crystallinity and interface quality of the tunnel barrier layer without exposing the magnetic layers to high temperatures that would cause PMA loss or metal diffusion, thus resolving the contradiction between achieving high crystallinity and maintaining magnetic layer stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a TMR of 200% or higher at a RA of 10, enhancing the storage and read performance of MRAM devices while maintaining thermal stability and reducing metal diffusion, thereby improving the overall quality of the magnetic layers.
Implementation Method 1
determining a tunneling magnetoresistance between the free layer and the reference layer through the tunnel barrier layer
Implementation Method 2
loss of perpendicular magnetic anisotropy (PMA) in the free layer and/or the reference layer
Data Source
AI summary
The disclosed technology generally relates to a stack for a magnetic random access memory device, for example, a stack including a magnetic tunnel junction with a high tunneling magnetoresistance ratio. In one aspect, the stack includes a substrate layer, a first electrode layer arranged on the substrate layer, and seed metal layer arranged on the first electrode layer, each layer having a [001] or [010] or [100] in-plane texture. The stack further includes a magnetic free layer arranged on the seed metal layer, a crystalline tunnel barrier layer arranged on the free layer, a magnetic reference layer arranged on the crystalline tunnel barrier layer, a pinning layer arranged on the reference layer, and a second electrode layer arranged on the pinning layer.