Vertical Resistive Memory Stack With Graphene and BN Layers
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Solution Overview
Problem
Existing vertical variable resistance memory devices face challenges with electron mobility due to surface roughness of insulation patterns between gate electrodes, and thick insulation layers are required to prevent leakage current, making it difficult to form vertical electrodes.
Innovation Solution
The use of graphene for gate electrodes and hexagonal or amorphous boron nitride (h-BN or a-BN) for insulation patterns, which reduces surface roughness and thickness, enhancing electron mobility and facilitating the formation of vertical electrodes with smaller dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick insulation layers are used to prevent leakage current, then leakage prevention is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the material parameter of the insulation layer from conventional materials to hexagonal boron nitride (h-BN), which has inherently superior electrical insulation properties. This material substitution allows achieving the same leakage prevention performance with significantly reduced thickness, resolving the contradiction between reliability and device complexity
Solution Approach 2:
The patent employs ultrathin h-BN insulation layers that can be precisely controlled in thickness, replacing the need for thick insulation layers. This approach uses a 'shorter' (thinner) object that achieves the same functional purpose with reduced dimensions, simplifying the overall device structure
2Reliability
If surface roughness of insulation patterns is reduced to improve electron mobility, then electron mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameter from conventional insulation materials to h-BN, which naturally provides an atomically flat surface with extremely low roughness. This material parameter change inherently achieves smooth surfaces without requiring excessively tight manufacturing tolerances, as h-BN's crystalline structure naturally resists surface defects
Solution Approach 2:
The patent uses composite material structures combining h-BN insulation layers with graphene gate electrodes. This composite approach leverages the complementary properties of both materials: h-BN provides both insulation and surface smoothness, while graphene provides high electron mobility, together resolving the contradiction between mobility improvement and manufacturing precision
3Quantity of substance
If vertical electrodes are made with smaller dimensions to improve integration density, then integration density is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent changes the surface energy and adhesion parameters by using h-BN as the insulation layer material. This creates an ideal interface for subsequent electrode material deposition, enabling precise formation of small-dimension vertical electrodes through standard fabrication processes without requiring advanced manufacturing techniques
Solution Approach 2:
The h-BN insulation layer acts as an intermediary that facilitates the formation of small-dimension vertical electrodes. Its atomically smooth surface serves as an ideal template for controlled material deposition, enabling precise electrode patterning at small dimensions while maintaining manufacturing feasibility through standard semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electron mobility and integration density by reducing resistance and preventing leakage current, while allowing for easier formation of vertical electrodes, thus enhancing the performance of the vertical variable resistance memory device.
Implementation Method 1
the mobility of electrons in gate electrodes may be considered
Implementation Method 2
first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN)
Data Source
AI summary
A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.