Ferroelectric Memory Cell With NCFET Gate for Low-Voltage High On-Current
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Solution Overview
Problem
Current non-volatile memory technologies, such as MRAM and FeRAM, face limitations in achieving high on-current at lower gate voltages, which restricts their performance and power efficiency due to the need for larger gate voltages to switch between resistance states in magnetic tunnel junctions and ferroelectric tunnel junctions.
Innovation Solution
The integration of a negative capacitance field effect transistor (NCFET) with a ferroelectric layer and gate dielectric layer, where the ferroelectric layer is in contact with the gate electrode and laterally wraps around it, generates a negative capacitance effect, allowing for increased on-current at the same or lower gate voltage by fine-tuning materials and thicknesses of the ferroelectric and gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional memory technologies (MRAM, FeRAM) are used, then data storage capability is achieved, but high gate voltage is required to switch between resistance states, resulting in high power consumption
Solution Approach 1:
The patent changes the electrical parameters of the gate by introducing a ferroelectric layer that generates negative capacitance. This modifies the gate voltage characteristics, enabling the memory device to operate at lower voltages while maintaining the ability to switch between resistance states, thereby reducing power consumption
2Productivity
If conventional memory technologies are used, then memory functionality is provided, but on-current is insufficient at lower gate voltages, limiting performance
Solution Approach 1:
The patent employs a composite gate structure consisting of a gate electrode, gate dielectric layer, and ferroelectric layer. This composite structure generates negative capacitance that amplifies the on-current at lower gate voltages, enhancing device performance without increasing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances on-current by a factor of 2 to 10 under the same gate voltage, reducing power consumption and improving memory device performance by enabling larger current output at lower gate voltages.
Implementation Method 1
the ferroelectric layer is in contact with the gate electrode and laterally wraps around it, generates a negative capacitance effect, allowing for increased on-current at the same or lower gate voltage
Data Source
AI summary
A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.