Memory Clock Generation Using Variable Delay to Reduce EMI
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Solution Overview
Problem
Semiconductor memory devices face increasing electro-magnetic interference (EMI) as they operate faster and occupy smaller areas, leading to potential circuit malfunctions due to short internal lines acting as antennas for internal clock signals, necessitating a solution to mitigate this interference.
Innovation Solution
A semiconductor memory device that modulates its internal clock signal based on operation frequency using a control voltage generation circuit and a voltage-controlled delay line to generate synchronization clock signals, reducing EMI by varying the clock signal frequency and synchronizing data output accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor memory device operates at higher speeds with shorter internal lines, then productivity and integration density are improved, but electro-magnetic interference increases causing circuit malfunction
Solution Approach 1:
The patent applies dynamics by making the internal clock signal frequency variable rather than fixed. The clock generation circuit dynamically adjusts the frequency of internal clock signals based on operating conditions, transforming the static clock system into a dynamic one that can adapt to reduce EMI while maintaining high-speed operation requirements
Solution Approach 2:
The patent changes the frequency parameter of the internal clock signal to resolve the EMI issue. By varying the clock frequency, the wavelength changes, preventing the internal lines from functioning as efficient antennas. This parameter change allows the system to maintain high-speed operation while reducing electromagnetic radiation through frequency modulation
2Object-generated harmful factors
If the internal clock signal frequency is modulated to reduce EMI, then electro-magnetic interference decreases, but clock signal stability and synchronization may be affected
Solution Approach 1:
The patent employs periodic action through controlled frequency modulation of the internal clock signal. The clock frequency is varied in a periodic manner that corresponds to data operation patterns, creating synchronized modulation that reduces EMI during critical periods while maintaining operational stability through structured, predictable frequency changes
Solution Approach 2:
The patent implements feedback mechanisms in the clock generation circuit that monitor operating conditions and adjust the internal clock frequency accordingly. This feedback control ensures that frequency modulation occurs in a controlled manner that reduces EMI while maintaining the necessary clock signal stability and synchronization for reliable memory operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases electro-magnetic interference both within and outside the semiconductor memory device by dynamically adjusting the internal clock signal frequency, preventing malfunctions and ensuring reliable operation at high frequencies.
Implementation Method 1
a voltage controlled delay line configured to generate an internal clock signal by delaying a reference clock signal by a time corresponding to the control voltage
Data Source
AI summary
A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.