RAM Shift Register With Embedded Addressing to Cut Circuit Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing shift register circuits require significant area and power due to the need for write and read control circuits to generate address signals, which can be inefficient in terms of implementation.
Innovation Solution
A shift register circuit design utilizing RAM with embedded addressing, where the RAM block stores and provides both write and read address signals, eliminating the need for separate control circuits and reducing the required area by integrating address generation within the RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate write and read control circuits are used to generate address signals, then the shift register can function properly, but the area and power consumption increase significantly
Solution Approach 1:
The patent merges the write control circuit and read control circuit into a single integrated control unit that generates both write and read address signals. This consolidation eliminates the need for separate control circuits, thereby reducing the overall circuit area while maintaining the shift register's data delay functionality.
Solution Approach 2:
The control circuit is designed to perform multiple functions: it generates both write addresses and read addresses, and can control both write and read operations within the RAM. This multi-functional approach replaces what would traditionally require separate dedicated control circuits, reducing area consumption.
2Reliability
If separate write and read control circuits are used to generate address signals, then the shift register can function properly, but the power consumption increases
Solution Approach 1:
By merging the write control circuit and read control circuit into a single integrated control unit, the patent reduces the total number of active components generating power consumption. The unified control circuit shares resources and reduces redundant power usage while maintaining full shift register functionality.
3Area of stationary object
If RAM with embedded addressing is used, then the area is reduced by eliminating control circuits, but the RAM block must store and manage both write and read addresses
Solution Approach 1:
The RAM block is designed to self-manage its addressing by storing both write addresses and read addresses within its own structure. The embedded addressing mechanism allows the RAM to automatically generate and manage its own address sequences for both write and read operations without external control circuitry, thereby reducing area while managing complexity internally.
Data Source
AI summary
Unlike prior RAM-based shift register circuits, the presently-disclosed shift register circuit does not require control circuits to generate write and read address signals. Instead, the presently-disclosed shift register circuit utilizes a portion of RAM to store and provide the write and read address signals. The write and read addresses are output from the data output port of the RAM, and received by the write and read address ports of the RAM. Advantageously, the presently-disclosed shift register circuit requires less area to implement because the need for write and read control circuits is eliminated.