Selectable Delay Paths for Memory I/O Timing Margin Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
At high operating speeds and low voltages, the timing margin for data capture in memories becomes sensitive due to smaller voltage differences and internal operating parameter variations, leading to issues in accurately capturing valid data.
Innovation Solution
Incorporating an adjustable delay circuit in the IO circuit to alter the timing margin by adjusting the propagation path of data strobe and data signals, using a plurality of delay unit circuits with different delay amounts, allowing for precise control of the timing margin during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory operates at high speeds and low voltages, then the productivity and power efficiency are improved, but the timing margin becomes smaller and more sensitive to variations
Solution Approach 1:
The patent implements adjustable delay circuits that can dynamically modify the timing margin based on operating conditions. The delay amount is configurable to compensate for reduced timing margins at high speeds and low voltages, allowing the system to adaptively maintain reliable data capture while operating at elevated performance levels.
Solution Approach 2:
The patent changes the delay parameter of signal propagation paths to adjust the timing margin. By modifying the delay amount in response to operating voltage and speed conditions, the system compensates for reduced timing margins without sacrificing productivity, effectively decoupling the trade-off between speed and reliability.
2Use of energy by stationary object
If the operating voltage is reduced, then the power consumption is decreased, but the voltage difference between logic states becomes smaller making detection more difficult
Solution Approach 1:
The patent applies delay adjustment before data capture to ensure sufficient timing margin even when voltage detection is more challenging. By pre-compensating for reduced signal transitions at low voltages through adjustable delay, the system maintains reliable detection without requiring higher operating voltages, thus preserving low power consumption.
3Reliability
If the timing margin is increased to ensure accurate data capture, then the reliability is improved, but the setup time and hold time requirements become more restrictive
Solution Approach 1:
The patent applies delay adjustment selectively to specific signal paths where timing margin is insufficient. Rather than uniformly increasing timing margins across all operations (which would reduce productivity), the adjustable delay circuits are targeted at critical paths, maintaining local reliability improvements without global time loss.
Data Source
AI summary
The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal line, an output circuit, and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to provide respective delay amounts that are different from each other, and where a first one of the plurality of delay circuits, which may be arranged most adjacently to the output circuit, being smaller in delay amount than other ones of the plurality of delay circuits. Each of the plurality of delay circuits may include an input node and an output node, and a selected one of the plurality of delay circuits connected at its input node to the signal line and at its output node to the output circuit, the rest of the plurality of delay circuits being disconnected from the signal line and the output circuit.