3D Memory TFT Channel Structure for Faster Write and Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies, such as volatile RAM and non-volatile FeRAM, face limitations in performance and efficiency due to planar channel regions in TFTs, which restrict write and read speeds and memory density.
Innovation Solution
The formation of three-dimensional channel regions in TFTs by recessing dielectric layers to expose word lines and depositing film stacks along these surfaces, allowing bit and source lines to contact the TFTs, enhancing channel region length and electric field strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar channel regions are used in TFTs, then the device structure is simple and easy to manufacture, but the write and read speeds are limited and memory density is restricted
Solution Approach 1:
The patent transitions from planar (2D) channel regions to three-dimensional channel regions by recessing dielectric layers and depositing film stacks along vertical surfaces. This dimensional change increases the effective channel length and surface area without increasing the planar footprint, thereby improving write and read speeds while maintaining manufacturing feasibility through established semiconductor processes.
Solution Approach 2:
The patent implements nested structures where tunneling strips, semiconductor strips, and film stacks are deposited sequentially within recessed regions formed by recessing dielectric layers. Each layer is nested within the previous structure, creating compact three-dimensional channel regions that enhance performance without requiring additional lateral space.
2Reliability
If three-dimensional channel regions are formed by recessing dielectric layers and depositing film stacks, then electric field strength increases and performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary recessing of dielectric layers before depositing the tunneling and semiconductor strips. This preliminary action creates the necessary three-dimensional structure in advance, allowing subsequent film deposition to conform to the recessed surfaces and form the enhanced channel regions without requiring additional complex processing steps.
Solution Approach 2:
The patent replaces mechanical planar fabrication with deposition-based formation of three-dimensional structures. By using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to form film stacks conformally on recessed surfaces, the process achieves complex three-dimensional geometries through chemical deposition rather than mechanical machining or planar lithography.
3Quantity of substance
If planar channel regions are used, then the fabrication process is simpler, but memory density and electric field strength are limited
Solution Approach 1:
The patent increases memory density by utilizing vertical space through three-dimensional channel regions. By recessing dielectric layers and forming film stacks along vertical surfaces, the effective channel length and active volume are increased without increasing the planar device footprint, thereby packing more functional elements into the same area.
Solution Approach 2:
The patent applies local quality enhancement by forming three-dimensional channel regions specifically at critical locations where performance improvement is needed. The recessed dielectric layers and deposited film stacks create localized regions of enhanced electric field strength and channel length, while other portions of the device maintain simpler structures.
Data Source
AI summary
In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.