3D FeFET RAM Structure for High-Density Low-Power Memory
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Solution Overview
Problem
Current memory devices face challenges in scaling down planar memory cells due to process technology limitations and reliability issues, leading to low write speed and high power consumption in 3D NAND memory, and high leakage current in phase change memory, necessitating the development of a high-speed and high-density storage class memory.
Innovation Solution
The implementation of a 3D Ferroelectric Field Effect Transistor Random Access Memory (FeFET RAM) device with a film stack having functional tiers, channel structures, and a ferroelectric film, where each channel structure includes a control gate, a memory film with a ferroelectric film, and a channel layer, and is separated by dielectric layers to enhance storage density and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled down to reduce die size, then manufacturing cost decreases and storage density increases, but process technology limitations and reliability issues worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) FeFET RAM structure, where memory cells are stacked vertically with multiple functional tiers arranged in the vertical direction. This dimensional change allows continued scaling and density improvement without suffering from the same process technology limitations that constrain planar scaling.
2Quantity of substance
If 3D NAND memory is used to achieve high density, then storage density increases, but write speed decreases and power consumption increases
Solution Approach 1:
The patent changes the fundamental storage mechanism parameter from charge-trapping (3D NAND) to ferroelectric polarization (FeFET RAM). This parameter change enables faster write speeds because ferroelectric switching occurs on nanosecond timescales compared to the slower charge pumping required in 3D NAND, while maintaining high density through the 3D vertical architecture.
Solution Approach 2:
The patent replaces the charge-pumping mechanism (mechanical/electrical system) used in 3D NAND with a ferroelectric field effect mechanism. The ferroelectric film directly switches polarization states under electric field control, eliminating the need for complex charge pump periphery and enabling faster, more energy-efficient writing.
3Quantity of substance
If phase change memory is used to achieve high density, then storage density increases, but leakage current increases and power consumption increases
Solution Approach 1:
The patent changes the storage mechanism parameter from phase-change states (amorphous/crystalline) to ferroelectric polarization states. This parameter change eliminates the high leakage current inherent in phase change memory because the ferroelectric FeFET structure maintains stable polarization states without requiring continuous power or generating significant leakage, while preserving non-volatility and high density.
4Length of moving object
If traditional planar FeFET RAM is scaled down, then device size decreases, but scaling becomes difficult due to process limitations
Solution Approach 1:
The patent moves from planar (2D) scaling to three-dimensional (3D) vertical stacking, where multiple functional tiers are arranged vertically. This dimensional change bypasses the process limitations that constrain planar scaling, allowing continued miniaturization through increased vertical integration rather than lateral compression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D FeFET RAM device achieves high storage density and low power consumption by utilizing ferroelectric materials for data storage, enabling faster write operations and improved endurance compared to traditional memories, while overcoming the limitations of planar FeFET RAM in scaling down.
Implementation Method 1
Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film
Data Source
AI summary
The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includes channel structures disposed in an array core region, wherein each channel structure extends through the film stack in the first direction. Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film. Each channel structure also includes a channel layer disposed on a sidewall of the memory film.