3D Ferroelectric Memory Structure for Higher Density With Lower Crosstalk
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current ferroelectric memories with a planar structure face challenges in scaling up storage density due to physical limitations, making it difficult to increase capacity and density.
Innovation Solution
A three-dimensional ferroelectric memory structure is developed, featuring intersecting bit lines, word lines, and ferroelectric capacitor pairs, with stacked capacitor configurations and integrated transistor connections to enhance storage density and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar structure is used for ferroelectric memory, then the manufacturing process is simple, but the storage density cannot be increased further due to physical dimension limitations
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional stacked structure by vertically stacking multiple ferroelectric capacitor pairs and transistors. This dimensional change allows multiple memory cells to occupy the same footprint area, dramatically increasing storage density while maintaining manufacturing feasibility through adapted fabrication processes
2Quantity of substance
If the storage density is increased, then the capacity is improved, but the manufacturing complexity increases
Solution Approach 1:
The memory structure is segmented into multiple identical stacked units, each containing ferroelectric capacitor pairs and transistors. This modular segmentation allows the complex three-dimensional structure to be manufactured using repeated fabrication steps, reducing overall manufacturing complexity despite the increased density
Solution Approach 2:
Multiple ferroelectric capacitor pairs are nested within a shared transistor structure, where several capacitors are stacked vertically and connected to a common transistor. This nesting reduces the number of transistors needed and simplifies the manufacturing process while achieving high storage density
3Quantity of substance
If multiple ferroelectric capacitors are stacked, then the storage density increases, but the crosstalk between capacitors increases
Solution Approach 1:
Insulating layers are introduced as intermediary elements between adjacent ferroelectric capacitors in the stacked structure. These insulating layers act as barriers that prevent electrical crosstalk between neighboring capacitors while allowing the capacitors to be closely packed for high density
4Quantity of substance
If the number of transistors is increased to control more capacitors, then the storage capacity increases, but the manufacturing time and costs increase
Solution Approach 1:
A single transistor is designed to control multiple ferroelectric capacitors simultaneously through shared control terminals. This multi-functional transistor reduces the total number of transistors needed in the memory array, decreasing manufacturing time and costs while maintaining high storage capacity
Data Source
AI summary
Provided are a ferroelectric memory, a three-dimensional ferroelectric memory, and a three-dimensional ferroelectric memory device. The ferroelectric memory includes a first word line, a first bit line, a first transistor, and a first ferroelectric capacitor pair. The first ferroelectric capacitor pair includes a first ferroelectric capacitor and a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor extend in a first direction. A control terminal of the first transistor is connected to the first word line. A second terminal of the first transistor is connected to the first bit line, and a first terminal of the first transistor is connected to upper electrode plates of the ferroelectric capacitor pair.