Digital Storage TRIZ Cases

Memory cells are grouped by erase count and refreshed at different recovery times to limit resistance drift while reducing wear and extending PCM life.

A spin-orbit torque path with separate read and write lines lowers MRAM write energy while reducing bit-line capacitance.

Adjacent SRAM cells place NFETs and PFETs on opposite stacked layers to cut cell area and improve IC miniaturization.

A floating-ground dynamic NAND sensing circuit cuts SRAM read stages and improves read access time while preserving data reliability.

Current-threshold write detection skips unnecessary redundant RRAM programming to cut power use and programming time while preserving reliability.

Dual state reference voltages widen STT MRAM read margins, helping the sensing amplifier read parallel and anti-parallel states accurately.

Local syndrome checks on a page subset estimate RBER and error weight in NAND memory without full reads, saving I/O bandwidth and power.

A mid-line boosting circuit senses rise and fall transitions to cut long metal line RC delay and speed memory pre-charge and discharge.

Two selectable pre-charge voltages let RAM use one level for reads and another for writes, improving storage capacitor charge accuracy across temperatures.

Compensatory voltages on adjacent word lines counter parasitic capacitance, reducing ferroelectric memory read and program errors.

Replacing DRAM capacitors with stacked transistors improves data stability, power efficiency, and integration density with simpler cell structure.

A bidirectional sense amplifier reads MRAM cells during charging and discharging, cutting read energy by 40% without slowing operation.

Defective via paths in 3D stacked memory are detected and bypassed with chip ID and signal switching to improve yield and cut routing cost.

An extra column plane lets memory fetch data, metadata, and ECC parity in one pass, cutting latency and power versus two-pass access.

Back-gate threshold control stabilizes NOSRAM bit line reading, cutting current fluctuation, power use, and read errors in dense cells.

ZQ-calibrated pre-drivers adjust output driving strength to stabilize memory slew rate across PVT variation without extra current draw.

Threshold-voltage sensing infers off-state temperature changes so read voltage can be adjusted before power-on for reliable memory operation.

Shared sense components and switching lines let multiple digit lines share sensing hardware, saving memory die area while preserving sensing.

Refreshing memory banks in staggered subsets bounds peak current, lowers PDN requirements, and reduces fabrication cost.

Reverse-bias switch circuits cut SRAM sleep leak current in p-type access transistor cells while simplifying power supply design.

Independent voltage control across three sub-word lines cuts leakage current in 3D memory cells while preserving electrical characteristics.

Continuous in-mode verification and two-stage pulse tuning speed resistive memory array programming while preserving target conductance accuracy.

Local DRAM die temperature sensors enable region-specific refresh timing to protect retention time under SoC hotspot conditions.

By forming the inductor during MRAM processing, this case cuts off-chip RF components, saves board area, and boosts magnetic energy storage.

A stacked ferroelectric capacitor and shared-transistor layout raises memory density while limiting crosstalk, energy use, and fabrication effort.

Ferroelectric dielectric layers in a vertical memory cell enable volatile and non-volatile operation with higher integration and reliable low-voltage sensing.

Reset feedback and delayed inversion shape an internal clock pulse width while cutting delay for high-speed memory synchronization.

Sequential LUT prefetch and register shifting enable parallel table lookup in memory banks, cutting latency, hardware load, and power use.

A floating comparator removes input capacitors to speed memory reads, cut power use, and preserve accuracy in shifted voltage domains.

Access-count tracking changes refresh periods for victim rows to prevent adjacent-cell bit flips while cutting unnecessary refresh power.

Separate BL and BLB charging circuits sweep different voltages to test DRAM sense amplifiers, measure offset, and check leakage.

Separate bit-line and sensing-line pre-charge voltages improve sensing margin while preserving data polarity balance in memory arrays.

Alternating ferromagnetic and coupling layers raise MTJ stability and anisotropy at smaller nodes while lowering critical current in MRAM.

Feedback-controlled current summing stabilizes MRAM write and read currents, reducing leakage effects and improving data storage reliability.

Iterative crossbar-based decoding factors hypervectors without exhaustive combination testing, cutting operations and improving noise robustness.

Polling and ALERT_n signaling let DRAM and the memory controller detect row hammer attacks early while limiting recovery overhead and power use.

Shared gain and access transistors with non-linear polar capacitors cut sense-line leakage and improve sensing margin in dense memory bit-cells.

Constant-current compliance linearizes ferroelectric multilevel programming, cutting read-out steps, power use, and variability sensitivity.

Ferroelectric channel layers around vertical conductive pillars enable nonvolatile data retention while preserving high memory integration density.

Varying gate oxide thickness and asymmetric source-drain structures lowers electric field stress, improving HCI and GIDL reliability.

A layered MTJ memory cell uses metal-oxide transistors and spin Hall switching to raise storage density while lowering power use.

Integrated selectors let SOT MRAM keep separate read and write paths while enabling dense crossbar arrays with lower energy use and better MTJ durability.

A vertical hole with concave sidewalls extends the channel and separates resistance layers, lowering program-erase bias and inter-cell interference.

A capacitance-variable selector in a stacked ferroelectric memory cell cuts unselected-cell disturbance and RC delay to improve speed and bit error rate.

Dummy bit lines matched to real bit lines improve MTJ resistance sensing, increasing read margin and read accuracy in MRAM.

A current-based read circuit with dual selectors stabilizes SOT-MRAM read margins by limiting MTJ heating and reducing read disturbance.

Offset dummy channels and local word line cuts reinforce 3D memory gate lines, limiting bridge collapse while preserving connectivity.

A 180-degree rotated switch layout between memory arrays preserves contact spacing and cuts dummy patterns in dense semiconductor I/O routing.

Using opposite transistor types in SRAM keeper and pre-charge circuits cuts area overhead while preserving bit line voltage during reads.

L-shaped conductive elements and a lateral phase-change layer let the memory cell fit one interconnect level while confining heat and reducing energy loss.