Bit Line Sense Amplifier Pre-Charge for Balanced Memory Sensing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently sensing data due to voltage imbalances caused by setting pre-charge voltages to ground or power supply levels, leading to data polarity issues and reduced sensing margin.
Innovation Solution
The memory device employs a bit line sense amplifier with separate pre-charge voltages for bit and complementary bit lines, and uses transfer gate transistors with different gate voltages to enhance data sensing by ensuring balanced voltage differences, utilizing isolation voltages to improve sensing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pre-charge voltage is set to ground voltage VSS or power supply voltage VDD, then the sensing margin is increased, but data polarity imbalance occurs
Solution Approach 1:
The patent applies local quality by providing different pre-charge voltages to different bit lines based on their specific needs. The voltage generator circuit generates multiple pre-charge voltage levels (VSS, VDD, and intermediate levels) and selectively applies them to different bit line pairs through control logic, allowing each bit line to have optimized local voltage characteristics for both sensing margin and polarity balance.
Solution Approach 2:
The patent changes the voltage parameter from a single fixed pre-charge level to multiple variable voltage levels. The voltage generator circuit dynamically selects and applies different voltage levels (ranging from VSS to VDD) to different bit lines based on the data polarity, thereby adjusting the electrical parameters to simultaneously achieve adequate sensing margin and polarity balance.
2Stability of the object's composition
If the pre-charge voltage is set to half the power supply voltage VDD, then data polarity balance is maintained, but the sensing margin is reduced
Solution Approach 1:
Instead of uniformly applying half-VDD pre-charge voltage to all bit lines, the patent implements local quality by allowing different bit lines to have different pre-charge voltage levels. The control circuit determines the appropriate voltage level for each bit line pair based on data polarity requirements, enabling some bit lines to use higher voltages for sensing margin while others use lower voltages for polarity balance.
Solution Approach 2:
The patent introduces dynamics by making the pre-charge voltage selection adaptive and time-varying. The voltage generator circuit dynamically adjusts the pre-charge voltage level applied to each bit line based on real-time data polarity conditions and sensing requirements, transitioning from a static fixed voltage approach to a dynamic adaptive voltage selection approach.
3Measurement precision
If separate pre-charge voltages are applied to bit lines, then sensing performance is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a voltage generator circuit that performs multiple functions: it generates various voltage levels (VSS, VDD, intermediate levels), selects appropriate voltages based on data polarity, and distributes them to multiple bit lines. This multi-functional circuit reduces overall system complexity compared to having separate voltage control circuits for each bit line.
Solution Approach 2:
The voltage generator circuit implements self-service by automatically determining the appropriate pre-charge voltage levels based on data polarity information and sensing requirements, without requiring external intervention or complex external control. The circuit autonomously manages the voltage selection and distribution, simplifying the overall control architecture.
Data Source
AI summary
A memory device including: a memory cell array including a first memory cell connected to a bit line, and a second memory cell connected to a complementary bit line; a bit line sense amplifier including a sensing bit line and a sensing complementary bit line; a first charge transfer transistor between the bit line and the sensing bit line; a second charge transfer transistor between the complementary bit line and the sensing complementary bit line; a first pre-charge transistor pre-charging the bit line and the complementary bit line with a first pre-charge voltage; a second pre-charge transistor pre-charging the sensing bit line and the sensing complementary bit line with a second pre-charge voltage; a first transfer gate transistor providing a first transfer gate voltage to the first charge transfer transistor; and a second transfer gate transistor providing a second transfer gate voltage to the second charge transfer transistor.