Leakage Current Sensing in Semiconductor Integrated Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Next-generation memory devices face challenges with leakage currents, which cause set/reset determination errors in variable resistive memory devices, limiting their performance and reliability.

Innovation Solution

A semiconductor integrated circuit device with a leakage current sensing unit and a determination circuit unit that measures and compensates for leakage currents, allowing for accurate data state determination by comparing voltage levels and currents during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If variable resistive memory devices are used to achieve high capacity and ultra-low power, then storage capacity and power efficiency are improved, but leakage currents cause set/reset determination errors

Engineering Contradiction:
Improveset/reset determination accuracyVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by measuring the leakage current of the resistive memory device before performing the set/reset operation. The leakage current measurement is conducted in advance to obtain a reference value, which is then used during the actual set/reset determination process. This preliminary measurement allows the system to compensate for leakage effects and improve determination accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the measured leakage current to adjust and refine the set/reset determination process. The leakage current measurement creates a feedback loop where the obtained leakage value is fed back into the determination logic, allowing for real-time compensation and improved accuracy in distinguishing between set and reset states.

Inventive Principle:
Principle #23Feedback

2Reliability

If leakage current sensing unit is added to measure and compensate leakage current, then read error reduction is achieved, but device complexity increases

Engineering Contradiction:
Improveread error rateVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the leakage current measurement function with the existing readout circuitry of the resistive memory device. By combining these functions into a unified circuit structure, the patent reduces the overall device complexity that would otherwise result from adding a completely separate sensing unit. The integrated approach allows leakage measurement and data reading to share common components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the readout circuit serve multiple functions: it can perform both the standard read operation and the leakage current measurement. This multi-functionality reduces the need for dedicated separate circuits, thereby limiting the increase in device complexity while still achieving accurate leakage compensation for error reduction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9455032B2Semiconductor integrated circuit device including a leakage current sensing unit and method of operating the same
Publication Date: 2016.09.27 SK HYNIX INC
  • US9455032B2 patent drawing
  • US9455032B2 patent drawing
  • US9455032B2 patent drawing

AI summary

A semiconductor integrated circuit device and a system including the same, configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The system a controller and a memory configured to interface with the controller. The memory includes a semiconductor integrated circuit device includes a leakage current sensing unit configured to sense a pure leakage current of a cell array according to a command of the controller; and a determination circuit unit configured to compare a voltage level of an input node with a reference voltage and determine a state of read data while in a read mode. The voltage level of the input node is decided by comparing an output current and a read current and the output current is decided by summing the pure leakage current and a reference current.